Research On Pulse Quenching By Single Event Effect In Nano CMOS Logic Circuits

With the rapid development of integated circuits(IC)technology to deep sub-micron,the influence of ion from radiation environment on its performance becomes more and more severe.Single-Event effect(SEE)caused by ion incidence has been one of the most important reasons of aerospace circuits failures.The feature size on the IC chip being shrunk to nanometer,thus charge sharing is enhanced by the decreasing transistor-to-transistor spacingwhen the ion strikes on the device.Some traditional circuit designs such as DICE,Guard ring,increasing distance between adjacent devices don't work because of multiple-bit upsets(MBU)by charge sharing.Pulse quenching effect based on charge sharing and multiple-bit upsets is an new way to defense single-event effect,but the research of layout design by pulse quenching can not explicit enough.This paper designs a series of experiments to find out the design rules of layout which can defense single-event effects.The main contents are as followings:(1)A 3D model of transistors in 90 nm for modeling and simulation is built with TCAD software.The distance between adjacent devices and the LET value of incidence ion varies to find out how these factors affect the pulse width of single-event effect.The simulation results indicate thattoo long distance between adjacent devices and too low the LET value lead to double peak voltage.According to pulse quenching effect,we can conclude that PMOS layout of OR gate and NMOS layout of AND gate are suitable for the new design via pulse quenching.And the minimal distance between adjacent devices and high LET value may make that devices are not sensitive to single-event effect.(2)Compared the result of ion incidence experiment of PMOS of OR gate in 90 nm with that in 65 nm,a conclusion can be made that with the decreasing of IC technology scale,the traditional layout of PMOS can well resist single-event effect.So the new design is not necessary for PMOS of OR gate.Also,comparing the different experimental results of NMOS of AND gate in 90 nm with that in 65 nm,a conclusion can be deduced that the new design plays a more significant role in the decreasing scale of IC technology.(3)The 3D model of transistors of 65 nm of combinational circuits is modeling for the simulation.There are two ways of combinational circuits to resist single-event effect.One is equivalent logic circuit,the other is the new design via pulse quenching.As the experiment showing,the new design via pulse quenching is more stable and easy.There are two suggestionsfor the design via pulse quenching: 1)the complicated circuits should change to the combination of OR gate and AND gate.2)when the layout shows cascade structure,the design via pulse quenching can be applied.At last,this paper makes some expectation for the design via pulse quenching in the smaller IC scale andother protectivedesigns for NMOS.