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Research On Pulse Quenching And Charge Sharing Effect Induced By Single Event In Nano CMOS Integrate Circuits

Posted on:2014-08-26Degree:DoctorType:Dissertation
Country:ChinaCandidate:J R QinFull Text:PDF
GTID:1268330422474188Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the rapid development of China’s aerospace science and technology, theresearch work of anti-radiation technology for advanced ICs is very urgent forspacecraft. With the continuous development of ICs technology, the number oftransistors integrated on a chip is increasing, clock frequency is increasing, theoperating voltage and the node capacitance are reducing, thus charge sharing hasbecome one of the main failure mode of nano ICs caused by Single Event.For nano technology, an ion trajectory has been able to cover more than one devicedue to the reduction of the device feature and the layout spacing, leading to multipledevices simultaneously collect charges. On the one hand, MBU led by the chargesharing effect makes radiation-harden methods such as DICE, TMR, are all facingfailure, thus inhibiting the charge sharing becomes one of the important mean ofinhibiting soft error in circuits. On the other hand, studies have shown that chargesharing may lead to the propagating SET pulsewidths reducing, thus enhancing thecharge sharing effect between the electrically adjacent transistors also becomes aneffective method. Layout structures, particles from the airspace, process doping, supplyvoltage, body bias and other factors will vary with the application environment, andunderstanding the influence of these factors on the charge sharing and Pulse Quenchingcan provide guidance for irradiation ICs design. In addition, due to the sensitivecharacteristics of SRAM cells to SEE, fully considering charge sharing mechanism ofsuch circuit in nanoscale and proposing effective reinforcement strategy are significantfor nano radiation-hardened design. Based on nano CMOS bulk silicon technology, thispaper investigated the physical mechanism of the charge sharing and radiation-hardentechnology in-depth, and mainly achieved the following aspects:(1) It is found that the SET pulsewidths can be greatly inhibited by minimizing thelayout spacing and signal propagation delay, which sheds new light on theradiation-hardened ICs design. The impact of key factors on Pulse Quenching wasstudied in depth, and the results show that the SET pulsewidths of propagation are not indirect proportion to the LET of incident particles, thus the defining of the LET thresholdshould be noted when SET/SEU occurs for the radiation-hardened design. Thecapability of anti-radiation meets the demand when LET is high but some soft errorsmay occur when LET is low. Therefore, radiation experiments should be focused onevaluating the LET that demonstrates the worst response to the circuit.(2) We have found that P+deep well doping and substrate doping can affect thecharge collection of the active and passive devices in nano-technology, thus affectingthe propagating SET pulsewidths in circuits. The propagating SET pulsewidths can bequenched by reducing the doping of P+deep well or increasing the substrate doping in the appropriate range. The effect of P+deep well doping and substrate doping on chargesharing and Pulse Quenching are investigated, which shows that the doping of P+deepwell mainly affects the bipolar amplification component of SET current, and thatchanging the P+deep well doping has little effect on NMOS but great effect on PMOS.(3) We have found that the SET pulse width propagating to subsequent stages in acircuit decreases with reduced power supply voltage, which runs counter to thepessimistic conclusion that ultra-low power applications are much more susceptible todisruption from particle strikes. Supply voltage dependency of SET propagation andmulti-node charge collection phenomena in CMOS ICs were also studied.(4) It is found that the sensitivity of SEE for P-hit is kept constant for the reversebody bias used in low power consumption technology while it reduces with theincreasing of body bias voltage for the forward body bias used in high speed circuits. Atthe same time, the susceptivity of SEE for N-hit is independent of the body bias. Theeffect of body bias on SET, charge sharing and Pulse Quenching were analyzed, and it isshown that the effect of body biasing on SET pulsewidths propagation is contrary withthe hit node when Pulse Quenching effect is considered.(5) It is found that the multi-node charge collection plays a key role on recoverymechanism, and it is shown that larger angle can bring about stronger charge sharingeffect, thus strengthening the recovery ability. The recovery mechanism of SEU wasstudied and a novel layout has been proposed to reduce the SEU vulnerability inSRAMs. The layout strategy proposed can gain both reliability and area cost benefitsimultaneously.
Keywords/Search Tags:Nano CMOS ICs, Charge Sharing Effect, Pulse Quenching Effect, Process Dependence, Voltage Dependence, Recovery Effect, SRAM
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