Research On Several Mechanisms Of Single Event Transient In Nano CMOS Integrated Circuits

With the rapid development of China’s aerospace science and technology, the research on the radiation-hardened advanced integrated circuits(ICs) has become the main concern in industry and academia. In nano-technologies, the probability of generation and propagation of single event transient(SETs) has increased due to the reduced nodal capacitance and gate delay, and the probability of SET being latched has risen with the increasing clock frequency. The SET induced soft error has become the key factor that determining the susceptibility of nano ICs to single event.The SET characteristic in nano ICs have significantly transformed. Firstly, the parasitic bipolar amplification effect plays an important role in charge collection and SET generation. Quantifying the contribution of parasitic bipolar amplification to PMOS and NMOS SETs respectively could be helpful for radiation hardening by design with high efficiency. The SET pulse widths dependent on the depth of charge collection and the area of electrical potential disturbance, both of which are directly related with the well structure. Secondly, multiple node charge collection has become one common phenomenon due to the highly increased transistor density. The circuit placement could significantly influences the multiple charge collection between adjacent cells, resulting in discrepancy in the circuit SET characteristic. In addition, the internal SET induced soft error in flip-flop cannot be ignored with the increased clock frequency. In nano-technology, the accuracy of numerical simulation is limited, and the experimental verification is highly required. Based on these concerns, this paper combined TCAD simulation and heavy-ion experiment, and investigated several mechanisms of the SET in nano CMOS ICs. The main works and contribution of this dissertation are as follows:(1) A novel test structure was proposed for quantifying the contribution of parasitic bipolar amplification to PMOS and NMOS SETs respectively. Using TCAD numerical simulation, the parasitic bipolar amplification was separated from the charge collection. A test chip was designed based on the simulation structure and heavy-ion experiment was performed. The test results show that the parasitic bipolar amplification significantly increased the PMOS SET pulse width, and the NMOS SET pulse width was slightly reduced due to the reversed bipolar amplification.(2) It is found that the PMOS SET pulse width is smaller in the triple-well structure than that in the dual-well. A “selectively implanted deep N well” structure was proposed based on the SET characteristic of PMOS and NMOS in triple-well and dual-well. The charge collection is deeper in triple-well for PMOS, but the well potential recovery is quicker when compared to the dual-well, which results a reduced parasitic bipolar amplification, thus the SET pulse width is smaller. The proposed “selectively implanted deep N well” can fasten the N well potential recovery without bring parasitic bipolar amplification in NMOS. The test results show that the proposed well structure has the narrowest average SET pulse width compared to the triple-well and dual-well when PMOS and NMOS were both considered.(3) It is found that the SET performance of two circuits identical in schematic could be markedly different due to the variety in circuit placement. The test results show that the horizontal placement design significantly reduces the SET pulse width and SET cross-section compared to the vertical placement design. Using TCAD simulation, the physical mechanisms behind was analyzed. The multiple node charge collection between the sequential two stages was reduced in vertical placement design due to the increased transistor spacing and well contact, resulting weak pulse quenching effect and increased SET pulse width.(4) It is found that the contribution of internal SET to soft error is higher in the triple-modular-redundancy(TMR) flip-flops(FF) than that in the unhardened DFF, and the frequency dependency is more apparent. The hardening design in TMR FF mitigates the direct upset and internal SETs in the latches, but the additional majority voter brings in more SETs. With the clock frequency increase, the advantage of TMR FF over DFF is reduced. The test results show that at 160 MHz the TMR FF is only 3.2 × harder than the unhardened DFF due to the internal SET.