Research And Chip Design Of MM-Wave Wide Band Frequency Divider For Silicon-Based Imaging Array Phase-Locked Loops

As one of the key blocks in MM-wave silicon-based image array frequency synthesizer (FS), millimeter (MM) wave wide band frequency divider (FD) can be used to divide voltage controlled oscillator (VCO) output signals to get stable local oscillator (LO) signals. Its performance greatly influences the FS’s performance so that it is significant to design a high speed, low power and alterable division ratios FD.According to ALMA Bandl (31.3-45GHz) silicon-based imaging array phase-locked loop (PLL) FS system design target, the operating frequency of this PLL is in 27.3-33GHz and the input reference frequency is set to 50MHz. Accordingly, the working frequency of the proposed MM-wave wide band FD should cover 27.3-33GHz and the division ratios of this FD should be 546-660. To realize 0.1 GHz frequency resolution ratio, a divide-by-2 FD followed by a programmable FD structure is adopted. To achieve the MM-wave wide band target, the proposed MM-wave wide-band FD is composed of an MM-wave wide-band divide-by-2 FD and a pulse/swallow (P/S) counter based programmable FD. Finally, an application in silicon-based imaging array phase-locked loops of this MM-wave wide-band FD is proposed. These chips are realized using 90nm CMOS technology with circuit design, pre-simulation, layout design, post-simulation, fabrication and chip test.The proposed MM-wave wide-band divide-by-2 FD is designed using two stages DCML latch structure and by using series peaking effect of spiral inductors and transmission line inductors, a current source DCML FD and an improved Razavi’s DCML FD are designed and the input sensitivity has been increased. What is more, by using the pseudo differential DCML layout design, it is the first time to increase Razavi’s DCML divide-by-2 FD’s working frequency to 40GHz. The measurement results show that this improved Razavi’s DCML FD enables high performance MM-wave wide band division with 300MHz-40GHz operating frequency,-40dBm input sensitivity,0.96mW power consumption for the least and 0.51×0.50 mm2chip area.The P/S counter based programmable FD consists of a divide-by-8/9 FD and a programmable P/S counter. The divide-by-8/9 FD is realized by using OR gate integrated CML synchronous divide-by-4/5 FD and asynchronous divide-by-2 FD. Post-simulation results show that the divide-by-8/9 FD can work from 10-20GHz with 50mV sensitivity and 3.84mW lowest power consumption. The working speed of the programmable P/S counter is increased by using simplified true single phase clock (TSPC) DFFs with reloadable function. The measurement results of this programmable FD shows that it can work at 7-20.5GHz input frequency range, consecutive 16～519 division ratios with 8.52mW power consumption, -23dBm input sensitivity and 0.575×0.475mm2 chip area.Based on the research of the improved Razavi structure DCML MM-wave wide-band divide-by-2 divider and the P/S counter based programmable FD, a 25-37GHz MM-wave wide-band FD has been designed and fabricated. The measurement results shows that this FD shares 32～1038 division ratios, the phase noise at 37GHz is less than-130dBc/Hz at 1MHz offset, the input sensitivity is better than-20dBm and the whole chip dissipates 17.88mW dynamic power consumption and occupies an area of only 0.730x0.475mm2. Utilizing the proposed MM-wave wide band FD, a CP based ALMA Bandl silicon-based imaging array PLL is designed. Measurement results show that the proposed PLL can work up to 34.027GHz, the phase noise with 556 division ratios is-91.3dBc/Hz at 1MHz offset and-107.6dBc/Hz at 3MHz offset, respectively. This PLL consumes 30.72mW power consumption and occupies 1.32×1.01 mm2 chip area.In conclusion, the proposed MM-wave wide band programmable FD can be applied for ALMA Bandl silicon based imaging array PLLs and other MM-wave frequency synthesizers.