The Research Of Divider Used In Harmonic Rejection System And Phase Error Detection

In the field of digital broadcasting, high integration and low cost of chip become the mainstream gradually, therefore, the preferable design is put forward higher requirements. In order to improve the integration of the receiver, its architecture widely used’zero-IF’ structure, and the application of harmonic rejection system application is gradually mature. However, a high performance receiver needs a frequency synthesizer to provide the local oscillator signal with low noise. Therefore, the design of divider in the receiver application plays an important role, also for the harmonic rejection mixer to get high-precision signals. Because of the mismatch is inevitable in the circuit manufacturing, resulting in the existence of phase error in signals, so it needs phase error detector and phase error correction circuit in the receiver to improve the performance of system.This paper introduces all kinds of dividers,and analyses the working principle of them, have an in-deep discussion about the current mode logic frequency divider used in the frequency above gigabit per second, and the injection locking theory of current mode logic frequency divider, then analysis the noise theory function of divider. The third chapter introduce harmonic rejection theory, summarizes the design experience of current mode logic frequency divider and theoretical guidance, compared the advantages and disadvantages,then correct an error in the theory of active negative capacitance, an improved ultra high speed prescaler and a divider by 4 is designed. The high speed prescaler operates at 25GHz-5 GHz, the supply voltage is 1,2 V, the DC power is 4 mW, and the value of FoM is 27.6. The divider by 4 to provide six local signals with 45 degree difference, its operation frequency is 1.6 GHz-800 MHz, at the voltage 1.8V, current 1.2 mA. Then the analysis summary of the phase error detection and error correction theory are given. And a phase error detector and a phase error correction circuit are designed. The phase error detector, use gilbert structure, operates at 400MHz-100MHz, the supply voltage is 1.8 V, and the DC current is 1 mA. The phase error correction circuit adopts a digital and analog correction scheme, the digital part adopts 8-bit current switch to correct phase error rough, the analog part adopts variable active negative capacitance to achieve phase error correction. All of designed circuits in this paper use SMIC 0.18-μm RF-CMOS process.