| In advanced processes,the static power consumption of chips is increasing.Therefore,designers use techniques such as multi-threshold voltage,body bias,and power shut-off to reduce static power consumption.Multi-threshold voltage techniques have the advantage of not increasing the difficulty of the physical design but require assignment algorithms that can effectively reduce static power consumption while meeting the timing constraints.However,the existing algorithms have the problems of limited types of assigned threshold voltages,poor static power consumption optimization,and long running time.This thesis proposes a multi-threshold voltage assignment method based on the simplified path set and cell delay-to-power ratio,which can effectively reduce the static power consumption of the chip time with acceptable running time.Firstly,the algorithm in this thesis simplifies the redundant timing information and uses the simplified path set as the timing constraint of the algorithm,which makes the algorithm feasible in time and overcomes the incompleteness brought by the simplification by expanding the path set.Then the path weights and cell weights are obtained by paths’ criticality and cells’ delay-to-power ratio;in the process of node-by-node replacement,the path weights and cell weights are used to efficiently find the cell with the greatest impact on the current timing and assign it to a lower-threshold voltage cell.Finally,the application area of the algorithm expands to scenarios with multiple standard cell libraries.In this thesis,the proposed multi-threshold voltage assignment algorithm is compared and validated with existing algorithms using a high-performance CPU as an experimental object.The 28 nm CMOS process used here supports three threshold voltages and three channel lengths,providing nine cell libraries with different latencies and power consumption.This thesis implements the complete physical design of the high-performance CPU,optimizing the proportion of low-threshold voltage cells in the synthesis,place,clock tree synthesis,and route phases.The existing CBLPRP,CAPCOM,PAA,and Prime Time algorithms are applied in the static timing analysis phase,as well as the proposed algorithm in this thesis.For the scenario with less than three types of cell libraries,the optimization effect and running time of this thesis’ algorithm are significantly better than those of CBLPRP,CAPCOM,and PAA algorithms;for the scenario with three threshold voltages and three channel lengths,the static power consumption of this thesis’ algorithm is reduced by 22.16% compared with the Prime Time algorithm,while the running time is increased by 60% to 8.4 hours.The experimental results show that the algorithm in this thesis can effectively assign multiple cell libraries to further reduce the static power consumption of the chip while ensuring chip timing. |
