Design And Research On Power Optimization For Chip Based Dual-threshold Voltage Assignment Algorithm

In recent years, along with the rapid development of integrated circuit, the processing speed and integration of the chip continue increasing drastically. Meanwhile the power dissipation gain more and more attention which brings chip temperature, heat dissipation and package a tremendous impact and challenge, especially in some portable electronic devices which require battery to maintain a long duration, such as PAD, mobile phone etc.. Hence, power dissipation is more and more significant for IC engineers, low power technology also has become the research hotspot.Based on the composition of power from the CMOS integrated circuit, we discuss the effect factors of dynamic power and static power and the contradictions between them. Low power technology for both dynamic power and static power is deeply analyzed in this thesis. Dynamic power optimization technology include gate-level power optimization technology, clock gating technology, multi-supply multi-voltage technology, dynamic voltage, frequency scaling technology and static power optimization technology include multi-threshold voltage technology, power shut off technology in which clock gating technology and multi-threshold voltage technology have little impact on each stages of circuit design and relatively easy to implement. A dual-threshold voltage assignment algorithm has been proposed in this thesis based on multi-threshold voltage technology to optimize the static power of the circuit. Under given timing constraint, our algorithm can analyze and distinguish the critical and non-critical paths effectively through initial optimization and accurate optimization in the static timing analysis. Our goal was to select a maximum number of nodes working at high-Vt such that the total static power was minimized in the circuit.Finish the physical design and verification from RTL codes to GDSII for the owned embedded CPU CK610under TSMC45nm process. In this process, challenges and difficulties under nanometer technology is also discussed and corresponding solutions are raised, such as power dissipation, IR-drop and crosstalk etc.. Meanwhile, power optimization design was carried out for this chip include clock gating technology and multi-threshold voltage technology. Comparison between the proposed dual-threshold voltage assignment algorithm and the existing algorithm in static timing analysis are performed. The results show that our proposed dual-threshold voltage assignment algorithm can reduce static power of the chip by16.6%and processing time can also be reduced95.2%. Our algorithm is a very effective method to reduce the static power consumption.