Physical Design Optimization Research Of High Performance Computing Chip Based On 16nmFinFET

HPC chip is the critical component of large-scale servers and super computers,its requirement for timing and power is more strict than other chips.Because the physical design directly affects the performance of chip,the physical design of HPC chip is very critical.This paper will finish the physical design of an HPC chip based on TSMC 16 nm Fin FET technology and propose an optimization method of multi-bit flip-flop with MSCTS(Multi-Source Clock Tree Synthesis).The method of combining FF(Flip-Flop)placement and CTS optimization for improving the design quality in HPC chip physical design is proposed.The main work are listed as follows:(1)Research the placement method of block,and propose FFs banking flow based on negative timing slack.Compare with the placement method only with single-bit FFs in kernel computing sub-block,experiment proves that sub-block's power gets a 3.23% reduction with a 1.5% augment in clock skew,and whole block gets a 3.90% power reduction.(2)We propose MSCTS based on two-level parallel driving buffer.Adopting the method proposed with the FF banking flow before in DDR4 PHY of this HPC chip.Experiment proves this optimized method could bring a 17.24% power reduction and greatly improve the clock tree quality.(3)Adopting FF banking with MSCTS method in the full chip physical design,it brings a 5.88% power reduction and achieves prospective design goal.The HPC chip will be mass production.