Low Power Design And Optimization Of Embedded SoC In Ultra-deep Submicron Process

Designing application-specific integrated circuits with System-on-a-Chip?SoC?technique has become an inevitable trend to develop embedded systems.Moreover,low power design for embedded SoCs is a general trend due to some key factors including cost,reliability,energy efficiency,market,battery capacity and so on.Aiming at low power optimization for the Central Processing Unit?CPU?and SoC,this thesis proposes two methods based on the multi-V_th CMOS technique,namely the leakage power optimization method on the hierarchical processing and clustering constraints,and the leakage power optimization method on the critical path numbers.Furthermore,to improve the power efficiency of SoCs targeted with the enhanced 8051 CPU and ARM-compatible CPU,respectively,two power management strategies are designed according to the application characterization of the system.One strategy is verified by taping out a USB device controller,the other is analyzed by simulating a sensor network SoC.The main content of this thesis can be summarized as follows.According to the development of embedded system,the importance of the low power design for SoC is introduced firstly.Then,based on the power model,the low power optimization methods are summarized.The clock gating,multi-voltage,multi-V_th CMOS technique and timing analysis technique related to the power optimization are particularly analyzed.After analyzing the related work on the multi-V_th CMOS assignment algorithms,an assignment method based on the hierarchical processing and clustering constraints is proposed.The method arranges the circuit nodes in multi-layers based on the critical path numbers,replaces the node-by-node optimization with the clustering processing,and processes the circuit nodes with the power delay correlation in clustering processing.The results show that this method can make adjustments to variable timing constraints and gain the leakage power reduction of 65%-73%.From the viewpoint of timing,an assignment method based on the critical path numbers is proposed.The method firstly archives the maximization of the leakage power reduction,and then handles the timing path violations with critical path numbers of the circuit node.The results indicate that this method can achieve the leakage power improvement of 66%-73%.Compared with the method based on the hierarchical processing and clustering constraints,this method can obtain better suitability in the case of increasing timing paths with violations.A power management strategy for SoC aimed at the enhanced 8051 CPU is presented.It is found that the USB device using the USB2.0 protocol only may lose power when it is actually inactive.To solve this problem and give external connector an interface to control the status of the internal system,a multi-trigger interactive self-resume power management strategy is proposed.The strategy is introduced from system strategy,architecture mapping to suspend-wakeup mechanism.The testing results demonstrate that the embedded power management unit shows better power efficiency,and the power decreases from 168.300 mW to 0.858 mW when the device switches from normal mode to idle mode.The proposed strategy minimizes the suspending current of the design and enhances the robustness of system.A power management strategy for SoC characterized with ARM-compatible CPU is presented.To utilize the system resources,a strategy with multiple work modes is provided.The strategy is implemented with power planning in power intent and power supply network controlled by power management unit.The power management unit includes bus interface,state control engine and wakeup control modules.In addition,to examine the correctness of the power control signals in timing and work modes in transitions,a unified hardware and software simulation platform is built,which consists of the establishment of a cross-compilation environment,firmware library and a voltage-aware simulation environment.The simulation results indicate that the power management unit can undertake the work mode transitions correctly.It can cut off the power of most modules in the deep-sleep mode and specific modules in the idle mode,and the system can work normally when coming back to the normal mode.In summary,the proposed method based on the hierarchical processing and clustering constraints and the proposed method based on the critical path numbers are both adaptive to the variable timing constraints,and can obtain the leakage power achievements by 65%-73%and 66%-73%,respectively.Compared with the related work,the proposed methods can get rid of the dependence on parameters and take into account the difference and critical characteristics of circuit nodes.The power management unit designed for the SoC with the enhanced 8051 CPU can promote the power efficiency of system,showing a power decrease from 168.300 mW to 0.858 mW when the device switches from normal mode to idle mode,and the power management unit designed for the SoC with the ARM-compatible CPU can control the power network properly.