The Research Of Low Power Physical Design And Verification Of OPENRISC SOC

Now,as the silicon-based integrated circuit feature size continues to shrink,the operating frequency and integration of complex SOC system continues to improve.With the increase of chip operating frequency and the number of transistors,power consumption of the chip urgently increase,while static power as the threshold voltage decreasing exponentially urgently increase,power consumption challenges highlight gradually.Therefore,SOC low power design technology in chip design aspects need for further research,and completion quality of physical design directly affects the chip performance,it is essential to research the physical design and verification of low power design technology.In this thesis,the power consumption source of the CMOS circuit is analyzed,and the influence factors of power consumption are determined.The key technology of low power consumption in physical design is further analyzed,and applied to OPENRISC SOC chip design project,based on TSMC 65 nm CMOS process,target operating frequency 300 MHz,,target total power of 100 MW,and area as far as possible optimization.Firstly,based on the optimization of multi threshold voltage technology,initial synthesize is completed and the timing requirements and power requirements of OPENRISC SOC design are analyzed.Design frequency can achieve 300 MHz target operating frequency,but the design power consumption over 100 mW target power consumption,need to use more effective low power technology.Therefore,with the front end design of the project to complete the application of OPENRISC SOC processor and peripherals scheduling computing requirements analysis,three kinds of working modes in the physical design stage using of different power management strategies are put forward.Then,the unified power format(UPF)is adopted to realize the low power consumption strategy of OPENRISC SOC.The system low power consumption synthesis is completed,and the system circuit with low power consumption policy related logics are generated.Multi voltage domain and power gating low power physical design and implementation of OPENRISC SOC is completed,and timing analysis meet the target operating frequency.Static functional verification and low power logic equivalence verification are completed.Finally,The power network integrity analysis of low power physical design and the power consumption analysis of the system are completed.The low power design total power consumption is 98 mW in complex task mode,82.9mW in simple tasks mode,and 77.4mW in vacant task mode.Compared with the traditional physical design of power 138 mW,respectively reduce the 28.98%,39.92% and 43.91%.Therefore,under the premise of meeting the target operating frequency,the low power strategy and physical design meet the requirements of the target power consumption of OPENRISC SOC chip design.