Low Power Design Of SOC Chip

Scaling of CMOS device dimension has made great improvement in both integration and performance of integrated circuits. But at the same time, with the increase of system complexity and the widely used mobile applications, power dissipation has become a serious constraint to IC development. Power consumption has direct impacts on chip package cost and system reliability. High power can also cause electro-migration, IR-drop and other problems, and makes circuits more unreliable. Furthermore, power challenges the design of power supply and ground, and analysis of reliability. When scaling down into deep sub-micro process, leakage power increases greatly and leads to many new problems. This makes research on low power design more and more important. All these drive more and more designers to make efforts on power estimation and optimization.System on a Chip is also a result of IC technology improvement. Whole system function implemented on a single chip is favorable to system's performance, area, power consumption, cost, harmony and reliability. It has become the trend of IC design. But on the other hand, the increase of area, integration and operation frequency make high power consumption and high power density be restrictions to SOC design. So it is a matter of great urgency to study low power of SOC design. Based on a really project, this paper does some innovative research on it.Supported by one national 863 project, High Performance Embedded CPU (2002AA1Z1040), we finished a SOC chip design and taped it out, which named ICT_E32. Based on this design, this paper will present the status of power estimation and optimization research, especially of SOC chip design, and give out some novel practical techniques of low power design. These techniques were successfully verified in ICTE32, and can be applied to other chip designs.The paper first introduces research background of low power area, basic conception of SOC chip and our ICTE32 chip; then summarizes the development and status of low power research work; and then analyzes both dynamic and static power of CMOS circuits. Starting with modeling various kinds of power resources, this paper provides many applicable techniques for power estimation and optimization. After that, aiming at the real design ICTE32, this paper presents the actual scheme of power optimization, and also gives out the simulation result. As the main innovative work of this paper, a new technique was brought forward as hierarchy power management, which based on the hierarchy character of SOC chip design. As the simulation result shows, it satisfies the power manage requirement while still meet scheduled performance requirement.At the end of this paper, some cross-field researches of low power and IC design are introduced, which ensures the integrality of the paper's research. This also shows that low power research is an independent field and is regarded by other research areas. Low power has become one of important domains in integrated circuit industry.