| Entering the deep sub-micron process, the power consumption is becoming increasingly serious. When entering the 90nm process, the static power of chip grows exponentially, which limits the development of handheld mobile terminals. This subject comes from a 40nm mobile processor chip project, in which the static power of Cortex-A7 quad-core CPU module is up to 106 mW, accounting for 51% of total chip static power consumption. High static power consumption shortens the standby time. This thesis optimizes the low-power design without affecting the design performance and effectively reduces the CPU module’s static power consumption.Based on the theoretical analysis of the low-power technology and quad-core A7’s own characteristics, we chose multi-threshold voltage technology and power shut-off technology to reduce the chip static power consumption. In the logic synthesis stage, based on multi-threshold voltage technology we designed a new logic synthesis strategies aimed at timing and power optimization. By contrast with the original program, the new design can effectively reduce static power consumption under the premise of meeting the design performance. Besides, according to the characteristics of multi-core multi-mode quad-core A7, we optimized the power shut-off strategy of CPU module and enriched the low power modes inside CPU. And we used UPF low-power design and back-end physical design to achieve a power-off policy and complete the relevant low power verification.Finally, this thesis completed the timing closure and the verification of CPU power module, the operating frequency of the CPU module reaches 850MHz, the area is 3.6×3.5 mm2, the static power consumption is 38mW, the IR drop of is less than 5%. The author participated in the design and implementation of low-power quad-core A7 module, we effectively reduced the chip static power consumption without affecting the design performance. The chip has been taped out successfully and serving smartphone market with good market reputation. |
