Research And Design On Memristor Based Ternary Combinational Logic Circuit

With the continuous development of modern information technology,the computer is expected to have a larger memory capacity and faster response speed,so there are further requirements for the design of integrated circuits.As a new type of nanodevice,memristor has low power consumption,memory characteristics,fast response speed and is compatible with CMOS technology.It has broad application prospects in the simulation of neuron synapses,logic operation,secure communication and non-volatile storage.At present,more research is based on binary logic circuit design.Compared with binary logic,ternary logic has more advantages,such as reduced design complexity,more data transmission on a set of lines,reduced chip area and greatly improved computing speed.Therefore,the ternary logic circuit based on memristor can effectively improve the information storage capacity and logic operation efficiency.The main research content of this paper is the ternary logic circuit design based on memristor,which mainly includes the following aspects:(1)The circuit design of ternary logic gates based on memristor is presented.Firstly,based on the basic characteristics of the memristor,the HP memristor,Yakopcic model and VTEAM model are simulated and analyzed.Then,based on the Yakopcic memristor model,the ternary logic gates is designed,including "AND" gate,"OR" gate,"NOT" gate,"NAND" gate,"NOR" gate,"XOR" gate and "XNOR" gate.The effectiveness of the ternary logic gates is verified by LTspice simulation software.(2)A series of ternary combinational logic circuits based on memristor are presented.First,the ternary encoder and the ternary decoder are designed according to the input-output relationship.Then,using the decoding function of the ternary decoder,the circuit designs of the ternary multiplier,the ternary half adder,the ternary half subtracter,the data selector and the data distributor are designed according to the logic expressions of the combined logic circuits.The validity of the designed ternary combination logic circuits is verified by the simulation analysis with LTspice software.(3)A method of two-input ternary logic circuit design,namely decomposition design method,is proposed.Based on this method,the circuit design of ternary multiplier and ternary half adder is designed.Firstly,the decomposition design method is described in detail,and then the ternary multiplier and ternary half adder circuits are designed by the decomposition design method.The correctness of each branch circuit design is verified on LTspice.Comparing the number of components between the designed circuits and the related circuits designed based on logic expression,the results show that the number of components used in the ternary multiplier designed based on the decomposition design method has decreased by nearly 50%,and the number of components used in the ternary half adder has decreased by nearly 40%,effectively proving the feasibility of the decomposition design method.