The Research On Radiation Hardening For Combinational Logic Circuit

With the progress of integrated circuit design process and the innovation of its design techniques, the integrated circuit feature size continues to decrease fast and the soft error induced by radiation in digital system is becoming more and more serious. The reliability of the digital circuit is under serious threat. Research on radiation hardening of integrated circuits has become one of the remarkable topics in microelectronic field at home and abroad in recent years. Early research shows that soft error rate in combinational logic circuit is negligible when compared to the soft error rate in the sequential logic circuit because of the three masking effects, namely logic masking, electric masking and latching window masking. However, as the feature size increasingly decreases following the Moore’s law, the three masking effects are weakened and the soft error rate in combinational logic circuit is continuously rising, exceeding the soft error rate in the sequential logic circuit in some circuits. The reliability and availability of the integrated circuit are seriously affected.To solve problems above, the main work is shown as the following several aspects.Firstly, the related concepts of integrated circuit soft error and the mechanism of soft error are studied, as well as the three masking effects - logic masking, electric masking and latching window masking. The generation and propagation mechanism of fault pulse and its impact on the reliability of integrated circuits are analyzed and the existing combinational logic radiation hardening technologies at home and abroad are analyzed and compared.Secondly, we analysis the characteristics of the CVSL gate and put forward "CVSL gate pair" structure, and then we verify its fault-tolerant performance. The double-storage mean and internal feedback structure of CVSL gate bring it stronger electric masking ability than ordinary CMOS gate, leading to strong immune ability to fault pulse propagation.Finally, we put forward the selective hardening strategy for combinational logic based on the structure of "CVSL gate pair". BFIT-an open source tool of the University of California is used to evaluate the soft error sensitivity of combinational logic node, on the basis of which the selection strategy for combinational logic selective hardening is presented. The strategy uses the proposed "CVSL gate pair" structure to replace the outputs which are connected to the soft error sensitive flip-flops directly. The reliability and availability of combinational logic circuit are effectively enhanced. We use HSPICE simulation tool to test the fault tolerance performance of designed circuit structure under different injection charge. We use BFIT tool to calculate soft error rate of each node in the circuits and evaluate the performance and overheads of the circuit after hardened. The experimental results show that the soft error protective rate is more than 90%, only adding 12.54% area overhead. As our hardening strategy arms only at the last two level of gates in combinational logic circuits, the delay overhead is negligible.