Design And Implementation Of A High Precision Phase-locked Loop Circuit Based On Sigma-delta Modulation

In the recent decade,most of the clocks in electronic communication field are generated by phase-locked loops(PLLs).For example,the data recovery in universal serial bus(USB)needs local clock with high precision and low jitter.As a result,PLLs are the foundation of accurate and stable data transmission in data transmitting system.However,a high-precision output clock of a PLL requires external crystal oscillator to provide reference clock.In order to save chip area and reduce costs,this thesis presents a design method for a crystal-free 480 MHz PLL which can be applied to USB2.0 transceiver.The thesis consists of the following parts.First,it presents the analysis of the concepts of fractional-N PLLs.Secondly,it describes the way of removing the external crystal oscillator according to real world application,which is to use a 12 MHz reference clock by fractional-dividing calculated internal RC clock frequency through USB communication protocols.Then,a linearized model by linearizing the building blocks of the PLL is proposed to analyse the transfer characteristics,stability and noise transfer characteristics.Fractional-N PLLs bring high precision and also produce a fixed spurious component.A Sigma-Delta modulation fractional-N PLL is presented in this thesis to get rid of the spurious component.Starting with the basic concepts of noise quantizing,oversampling technique and noise shaping,the theory of Sigma-Delta modulation is then described.Finally,it analyses the transfer characteristics of a Sigma-Delta modulation circuit based on MASH 1-1-1-1 structure.Detailed analyses and design procedures of PLL building blocks are presented.The structure of the analyses is composed of the following parts.First,it presents a flip-flop circuit for Phase-frequency Detector(PFD)and a way of minimize the effect of dead-zone by adding delay cells at the feedback reset path.Second,the issue of charge-sharing and current mismatch is analyzed and a way to minimize the charge-sharing effect is proposed.Third,a high frequency noise rejecting third-order loop filter's component parameters are calculated through PLL's open loop transfer function.At last,a voltage-controlled oscillator(VCO)is proposed with high supply and substrate noise rejection capability using dynamic biasing circuit and symmetric load Maneatis delay cell.The PLL's performances are verified and layout drawn using SMIC55 nm process,through Cadence Spectre.In circuit layout perspective,the secondary effects of layouts are presented.For the sake of saving chip area,a method of increasing the capacitance of a capacitor is proposed,which has zero process cost.The total floor plan is also presented.At the end of the thesis,test and analysis are performed to the manufactured chip.The feasibility of a crystal-free Sigma-Delta fractional-N PLL is verified.Under different supply voltage and temperature circumstances,the PLL presents timing jitter less than 20 ps and consumes power less than10.3mW.