Research And Design Of Fractional-N Phase-Locked Loop Based On Sigma-Delta Modulator

Wireless communication technology plays an important role in today's information transmission.Its development is closely related to phase-locked loops(PLL),and phase-locked loop technology has received more and more research as a result.The phase-locked loop provides a local oscillator signal for modulation or demodulation in the wireless transceiver,and it can also provide a clock signal for digital circuit systems.The performance of a phase-locked loop is very important to the entire system,so a high-performance phase-locked loop must have the advantages of low phase noise,low spurious,low power consumption,wide tuning range and must be a highly integrated solution.In this paper,a 4959.02 MHz phase-locked loop used in the receiver of the BD1 is designed,it has a good phase noise performance and low power consumption.In the first,the article introduces the research background of PLL,describes the research status in our country and abroad,and introduces the current advanced PLL products.Then this article introduces the working principle of the PLL,analyses each circuit module of the PLL,analyses the phase noise in the s domain,and models the phase noise used MATLAB.Next introduces the methods to realize fractional-N PLL,chooses Sigma-Delta modulator(SDM)as the method used in this PLL,introduces the principle of SDM,and compares SDM of different structures.List the advantages and disadvantages of SDM in terms of output cycle length,circuit stability and power consumption,and chose the SDM structure used in this article.This article uses a linear shift register to generate a pseudo-random sequence,and add a jitter signal to the SDM to achieve the purpose of reducing spurs.Finally,the overall phase-locked loop circuit is simulated,and the corresponding parameters are measured,so that the design meets the preset indicators.The circuit is fabricated using TSMC 130 nm RF CMOS process.The supply voltage is 1.5 V.Tested results show that the phase noise at 4959.02 MHz frequency is-115.9 dBc/Hz@1MHz,the power consumption is 14.25 mW,and the tuning range is 4.56 GHz-6.47 GHz.