Design Of Phase Locked With Low Noise And Low Jitter Based On 40-nm CMOS Process

Wireless signals should be transmitted according to a strict and specific frequency in a wireless communication circuit.Therefore,a clock generation circuit called frequency synthesizer is needed to produce pure clock signal in RF transceiver system.Usually we choose indirect synthesis,that is,phase-locked loop system implementation.The PLL is a negative feedback loop realized by frequency divider and a high gain feedforward path including an ideal integrator to realize the frequency and phase locking of the oscillator after frequency divider by reference clock.Phase noise is the most important performance indicator of the frequency synthesizer phase-locked loop,and a low noise and jitter phase-locked loop is required in both RF and digital clock.This paper studies the phase noise of low-loss distribution charge pump and oscillator,and the bandwidth of loop based on the analysis of the working principle and noise characteristics of each module of PLL.Firstly,a high-speed phase discriminator and a charge pump with wide matching range and low mismatch current are designed to achieve a low equivalent output noise current and reduce the noise in the loop bandwidth.Then,an inductor and capacitor-based voltage-controlled oscillator with low noise and high linearity based on extra linear compensation module is designed to reduce the external phase noise of the loop bandwidth,and the oscillator with high linearity is used to stabilize the loop bandwidth of the phase-locked loop,so that the integrated area of the power spectrum density of the phaselocked loop noise is relatively stable,so as to maintain low random jitter.Finally,the loop characteristics and the noise transfer function of each module are analyzed,and the phase noise and jitter of the whole phase locked loop are obtained.TSMC40nm technology is used to complete the design and simulation of each phase locked loop module and layout in this paper.The simulation results show that the output deterministic jitter is 7.41ps,and the power consumption is 3.6mW,The area is 337×324μm2 and the FoM value is-260.7dB under the frequency of 4GHz.