Reserch And Design Of A Wide-Temperature-range PLL Frequency Synthesizer

In today’s society,the development of information technology has become a reality with the progress of human technology.This grand digital achievement ultimately benefits from the vigorous development of integrated circuits,which are the physical carriers of digital algorithms,mainly based on silicon-based semiconductors.Therefore,with the requirements of informatization and digitalization,the application scope of integrated circuit products and different environmental disturbances also make increasingly updated requirements,which also makes the performance requirements of the clock signal,as the"heart"of electronic circuit drive,increasingly high.The integrated Phase-Locked Loop(PLL)is commonly used to construct a clock signal frequency synthesizer to complete the synthesis of clock signals,thus providing accurate clocks that meet the requirements for other parts of the electronic circuit system.At the same time,due to the requirements of the use environment,researching the integrated PLL products under high-temperature and high-pressure application conditions is of great significance for expanding the application scope of existing integrated circuits.This paper discusses the 180nm high-temperature CMOS process and related topics in the research group’s underground oil and gas exploration.The research provides clock excitation signals for the oven controlled MEMS oscillator(OCMO)in the overall MEMS digital detector system.It also designs an integrated phase-locked loop(PLL)chip that can operate stably over a wide temperature range,including normal and high temperature conditions.The selected architecture for the system model design is the charge pump PLL(CPPLL),with a chip area of 0.49mm~2,an operating voltage of3.3V,and an average dynamic power consumption of 9.88 m W.The input reference signal frequency is 8MHz,and the maximum division ratio is 30.This can output a clock signal with a maximum frequency of 240MHz,and different frequency signals with continuous integer division ratios of 14 to 30can be output.The lock-in time is about 28μs.At the frequency deviation of10MHz of the maximum output frequency of 240MHz,the phase noise is-116.26d Bc/Hz,the RMS jitter is 2.61ps,and the maximum reference spurious is-17.26d B.The chip can output a stable frequency signal with a temperature coefficient of 70.67ppm/℃between the operating temperature of-40～175℃.After pre-simulation and post-simulation,The tapeouts of the chip have been manufactured.Chips were tested and the results showed that the proposed temperature compensation structure meets the preset indicators.This confirms,to a preliminary extent,that this design can achieve a functional and stable PLL system design across a wide temperature range.