Analysis And Design Of High-performance Charge-pump PLL

High-performance frequency synthesizer is one of the key components in the modern sophisticated electronic equipment, it has an important impact on the performance of system. With the development of communications, radar and measurement technology, the demands to the stability, the purity and the lock range of frequency source are stricter and stricter. Among PLLs, the charge-pump PLL(CPPLL) having the advantages of easy integration, high lock speed, wide lock range, has become a widely used structure nowadays.The issue is a lateral cooperation project with Miartech (Shanghai) Co., Ltd., one chip of this company needs two external crystal oscillators, The frequency is respectively: 32.768KHz and 22.118MHz. Author's work is to achieve 22.118MHz clock for internal circuits with the 32.768KHz crystal oscillator through PLL frequency synthesizer technology, thereby reducing external circuit chip cost.According to top down design method, the paper detailedly introduces the entire project development process from the system-level to the circuit-level design. In the system-level design, the analysis focuses on the working principle of the CPPLL, establish sub-module design requirements of CPPLL and then establish systematic behavioral model to validate and optimize the system design parameters with Simulink tools. In circuit-level design process, this paper has given the design process of CPPLL's module circuits,including frequency/phase detector, charge pump, VCO, frequency divider, the circuit design process has focused on low power design, used the circuit structure such as m sequence code generator and divide-by-2 configured by source-coupled logic (SCL) to lower overall power consumption. Verified by simulation, all the sub-module circuits meet the design requirement.