| Wireless communication technique had a rapid improvement since the1960s with thehelp of the integrated circuit. And in the wireless transceiver chip, the key technology ishow to realize a high performance frequency source. Since the charge pump phase lockedloop has the characteristic which have a simple structure and low phase error, it widelyused in the frequency synthesizer to generate a accurate frequency source for wirelesstransceiver chip.ASK modulation technology is a frequently used wireless communication modulationtechnology. In this paper, we designed a charge pump PLL frequency synthesizer whichused in ASK modulation wireless transceiver chip. The input reference frequency is9.375MHz~14.0625MHz, which have a300MHz~450MHz output frequency after thirtymultiplying, and this frequency synthesizer is used to provide a accurate local carrier forASK modulation wireless transceiver chip.The paper begin with the basic theory and discuss the basic principle of CPPLL indetail firstly. And then we put forward a charge pump PLL based on the actual applicationrequirements. The entire charge pump PLL contained five parts which they are PFD,voltage control oscillator, charge pump, loop filter and frequency divider. In the CPPLL,we have used the OPMAP bootstrap charge pump and large delay PFD to decrease theinfluence of the non-ideal factor.In order to eliminate the impact of power supply voltage fluctuations, we provide aLow Dropout Regulator to power the CPPLL in this paper. The LDO mainly consists oftwo parts: the bandgap reference and error amplifier. And we design these two partsattentively to provide a accurate power signal.Ultimately, the circuit is designed based on XFAB0.35um technology. And we haveused the Specture to simulate the circuit. The simulation result show that there is a 300MHz~450MHz output as the input frequency between9.375MHz and14.0625MHz,and the PLL locked time is about5us. And the PLL output frequency fluctuations areacceptable when the PLL locked. |
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