Design And Implementation Of A Sigam Delta ADC With 14-bit And 256 Times Oversampling

With the rapid development of technology,people are paying increasing attention to their physical health,leading to the emergence of numerous wearable electronic devices.These wearable electronic devices convert analog signals related to human health into digital signals for storage and display.The Analog-to-Digital Converter(ADC)serves as one of the core components of wearable electronic devices,and its performance directly determines the accuracy of human health monitoring information.Currently,mainstream high-resolution ADCs often use Sigma-Delta architecture,which consists of the analog modulator and digital decimation filter as the core functional modules.The analog modulator uses oversampling and noise shaping techniques to move the noise of the in-band signal to the out-of-band.The digital decimation filter filters the high-speed,low-bit signal stream from the analog modulator and generates a low-speed,high-bit data output.This article focuses on the research of these two parts.Firstly,a system-level modeling of the analog modulator of the Sigma Delta ADC was performed based on the 14-bit resolution specification of the ADC.The structure employed a Cascade of Integrators with Feedback(CIFB)configuration,with an oversampling ratio of 256 and a quantization bit of 1.The modeling of the analog modulator was accomplished using Matlab software,and the model was simulated.A parameter scanning simulation method was utilized to determine the specific parameters that satisfy the specifications.Based on the identified parameters,the design of the modulator circuit was carried out,including the integrators,feedback DAC,quantizer,and two-phase non-overlapping clock.Finally,functional simulations were conducted on the analog modulator system.Second,a three-stage cascaded digital decimation filter that matches the preceding analog modulator is designed.The decimation ratio and order of the digital decimation filter are determined based on the parameters of the analog modulator.The overall digital decimation filter consists of a cascaded integrator comb(CIC)filter,finite impulse response(FIR)compensation filter,and half-band filter.The CIC filter is implemented with a decimation ratio of 32 and 3 stages.The compensation filter has a decimation ratio of 4 and reduces the passband attenuation of the preceding CIC filter to below 0.01 dB.The half-band filter provides good stopband attenuation and is used as the final stage.The CIC filter uses a transpose structure to operate some circuits in the low-frequency region to reduce power consumption.The multiplier sharing structure is used for the last two stages to reduce circuit area,and the canonic signed digit(CSD)encoding is used to reduce power consumption.To ensure the correct functionality of the digital decimation filter,a verification platform is built based on the Universal Verification Methodology(UVM).Functional coverage and code coverage analysis are conducted to ensure the correctness of the entire filter.Finally,the digital backend flow is applied to the entire digital filter,including DC synthesis and layout.The layout design is based on the Huali 110 nm process library.The digital layout and analog layout are integrated together,resulting in a final layout area of 1172×700μm2,power consumption of approximately 2.5mW,signal-to-noise ratio of 81.34 dB,and effective number of bits(ENOB)of 13.22 bits.