Sigma-delta Adc Digital Decimation Filter Design And Asic Implementation

The research, design and ASIC implementation of digital decimation filter in Sigma-Delta Analog-to-Digital converter are introduced in the dissertation.As the analog interface component, Sigma-Delta Analog-to-Digital converter in modern digital communication system and digital signal processing system, with advantages of high resolution and high cost performance, has been widely and popular used.Digital decimation filter is an important component of Sigma-Delta Analog-to-Digital converter. It transforms the digitally modulated signal from low resolution at high sampling rate to high resolution at Nyquist rate. Generally, the modulator circuit in a Sigma-Delta Analog-to-Digital converter, mainly decides the design resolution and transition rate, but, the transition rate, chip area and power dissipation of the digital decimation filter also have large influence on the performance of Sigma-Delta Analog-to-Digital converter.This dissertation presents an efficient design and implementation of a digital decimation filter with a down-sampling ratio of 256, which can be used in 2-1-1MASHΣΔmodulator circuit. The proposed digital decimation filter consists of Cascaded-Integrated-Comb (CIC) filter and three-stage cascaded Half-Band (HB) filter. Adopting a new five-stage cascaded structure with a down-sampling ratio of 32, which reduces the number of decimation circuits and leaves decimation to be done by the circuits afterwards, the CIC filter can decrease the cost of hardware. Each Half-Band filter that with a down-sampling ratio of 2, use Canonic Signed Digit (CSD) number as its filter coefficient, can reduce the computation and complexity during its implementation, and also can transform the multiplication to addition or subtraction, to decrease the cost of hardware. The whole digital decimation filter is designed and implemented through the manner of multi-stage, multi-rate signal processing.The design and ASIC implementation of digital decimation filter start from MATLAB system simulation, VHDL RTL coding, Synopsys VCS RTL simulation, Synopsys Design Compiler synthesis, Synopsys PrimeTime static timing analysis, and Synopsys Astor place and route. The whole design fabricated in the process of JAZZ 0.35μm CMOS technology with chip area 2.1×2.1mm2. Through post-simulation, the SNR (Signal to Noise Ratio) is 110.41(dB), and ENOB (Effective Number of Bits) is 18.046 bit.