Research And Design Of Phase-Locked Loops For Infrared Focal Plane Clock Generation Circuits

High-quality clock signals are very important for digital circuits and mixed digitalanalog integrated circuits.Digital circuits rely on accurate timing logic to ensure the correctness of work,and the basic component of timing logic is the clock.Phase-locked loop frequency synthesizer as the most common frequency synthesis technology has the advantages of high output frequency,wide tuning range,good stability,noise rejection capability,etc.,and is therefore widely used in clock generation circuits.This thesis designs a charge pump phase-locked loop based on the SMIC 0.18μm CMOS process to provide a clock signal for an uncooled infrared focal plane readout circuit to meet its clocking scheme.The current mainstream readout circuits use columnlevel ADCs for analog-to-digital conversion,which places high demands on the driving clock frequency and quality.To meet a wide range of applicability and reduce design costs,the output frequency range of the phase-locked loop needs to reach 240 MHz～720 MHz,power consumption is less than 10 m W,and clock jitter is less than 5 ps.Starting from the application requirements of readout circuits,this paper provides a generally applicable system-level design methodology for phase-locked loop circuits and develops the entire design flow.To reduce the circuit design cycle,a behavior-level simulation model is built to quickly adjust and optimize the macro parameters and provide guidance for subsequent module circuit design.At the system design level,a mathematical model and a graphical solution to the problem of phase noise optimization in phase-locked loops are implemented to suppress the overall loop noise by adjusting the loop bandwidth.At the module design level,the voltage-controlled oscillator and charge pump are the design focus of the charge pump phase-locked loop.For the design requirements of wide tuning range and low phase noise,this thesis proposes a switchcontrolled dual oscillator structure based on an improved pseudo-differential unit.Simulations show that the use of two independent voltage-controlled oscillators can achieve a tuning range covering 180MHz～800MHz with small changes in power consumption and gain sensitivity.In addition,for the traditional charge pump dynamic mismatch problem,this thesis uses a source-switched charge pump based on dual op-amp clamping to improve the charge sharing problem,and adds additional pull-up and pulldown MOS tubes to speed up the switch-off speed of the charge pump,which greatly reduces the periodic voltage spikes on the control voltage.To address the problem of phase noise accumulation and delay accumulation generated by the serial D flip-flop in the divider,this thesis designs a retiming circuit and an improved cycle detection circuit in the divider circuit,so that the phase noise and delay of the output signal of the whole divider are determined by the end D flip-flop only.This phase-locked loop operates at 1.8 V supply voltage,except for VCO,which is separately powered by the regulated isolator.The output clock RMS jitter is 2.79 ps and power consumption is 6.35 m W at output frequency 320 MHz and 3.08 ps and 7.28 m W at output frequency 640 MHz,which meet the design requirements.