Analysis And Design Of High-Speed Continuous Integer Frequency Division Phase-Locked Loop Circuit

For high-speed analog chips such as ADCs(Analog to Digital Converter),clock distributors,DACs(Digital to Analog Converter),etc.,a clean and low-jitter clock is an essential building block.Since the oscillation frequency of existing crystal oscillators is generally not high,using a crystal oscillator as the reference clock will greatly reduce the response speed of the entire chip’s critical modules.Therefore,a PLL is needed to provide a more stable,accurate and high-speed clock signal.In addition,by using the PLL’s multiplication or division function,the frequency of the input clock signal can be changed,improving the applicability and flexibility of the analog chip and further reducing the cost of electronic devices.This thesis is based on the actual project needs of the company and designs a highspeed continuous integer division phase-locked loop circuit for application in ADC chips.Under various processes and temperature changes,the phase-locked loop outputs a stable clock signal.The main research content and achievements are as follows:(1)A traditional R-S type phase/frequency detector(PFD)is used,and a 3-bit adjustable delay chain structure is added to solve the "dead zone" problem of the PFD under different input frequencies,while minimizing the opening time of the charge pump in the later stage to reduce the noise injected into the circuit by the charge pump.After in-depth analysis of the charge pump’s structure and various non-ideal effects,effective solutions are proposed for these non-ideal effects.This article uses current self-calibration technology to counteract the influence of different processes and temperatures on the charge pump’s up and down currents,achieving a matching accuracy of 0.05%.(2)Designed a high-frequency range LC-VCO circuit with a high tuning rang.A capacitor array with 512 sub-bands and a tail current array with 2048 sub-bands are designed.At the same time,an automatic frequency control(AFC)algorithm based on the bisection method is designed.The AFC circuit including two modules: automatic band control(ABC)and automatic level control(ALC).This can achieve a series of processes from VCO power-on initialization to frequency band locking and output signal peak stability within 20,000 reference clock cycles.At the same time,the frequency band coverage rate can reach more than 50%,and the phase noise is-111 d Bc/Hz.This project uses TSMC 28 nm process.According to the simulation,the tuning range of this phase-locked loop is 6.25-13.78 GHz.Under the condition of an input reference frequency of 400 MHz and an output clock of 12.4GHz,the phase noise of the phase-locked loop output is about-109 d Bc/Hz@1MHz,and the locking time is less than25μs.After chip testing,the phase-locked loop functions normally,and the phase noise is approximately-102 d Bc/Hz@1MHz after conversion,which is slightly different from the simulation fitting result but better than the design target.