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Design And Implementation Of Reconfigurable FIR Filter Based On FPG

Posted on:2022-01-18Degree:MasterType:Thesis
Country:ChinaCandidate:J H GuFull Text:PDF
GTID:2568307067982109Subject:Integrated circuit engineering
Abstract/Summary:PDF Full Text Request
FIR filter is widely used in digital signal processing system because of its stability and strict linear phase characteristics.Reconfigurable FIR filter can change its function in real time to meet different filtering needs,which has become a research hotspot.However,the traditional reconfigurable FIR filter has the problems of complex reconstruction mode or high resource consumption.In order to solve these problems,a new reconfigurable FIR filter is proposed by combining the optimized distributed structure with the reconfigurable look-up table CFGLUT5.It can realize four filtering functions: low-pass,high pass,band-pass and band stop,and dynamically switch the filtering function by dynamically changing the partial product in CFGLUT5.Based on Xilinx latest Artix-7 core,FPGA implementation of reconfigurable FIR filter is completed.The reconfigurable FIR filter is reconstructed by updating the partial product in CFGLUT5,so the reconstruction method is simple.In the process of reconstruction,the partial product stored in ROM is written into the CFGLUT5,while FPGA reads and writes the internal lookup table and memory very fast,so the reconstruction time will be very short.The resource utilization rate after comprehensive optimization is less than 10%,so the resource consumption is low.In addition,a RISC-V CPU developed by this paper is used as the reconstruction controller of the filter.RISC-V CPU outputs the I / O signal as the external control signal of the filter,which can effectively and conveniently control the filter reconstruction function.The filter system composed of reconfigurable FIR filter and RISC-V CPU is implemented by FPGA,the system has a maximum clock frequency of 180 MHz,a circuit area of 21.6 mm2,and a power consumption of 21.4mW.Compared with common reconfigurable filters,the maximum clock frequency is increased by 37%,the circuit area is reduced by 40%,the power consumption is reduced by 36%,and the performance is greatly improved.In addition,the function simulation and onboard experiment of the reconfigurable FIR filter are carried out,and the filtering effect is good.The reconfigurable FIR filter designed in this paper has the advantages of convenient control,short reconstruction time and low resource consumption.It can be widely used in the fields of communication,radar,speech processing,image processing and so on.
Keywords/Search Tags:FPGA, distributed architecture, FIR filter, reconfigurable, RISC-V CPU
PDF Full Text Request
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