Based On The Password Chip Design Reconfigurable Architecture And Its Fpga Implementation

This paper systematically presents the whole design process of a cryptogrammic chip based on reconfigurable architecture.Firstly it begins with a brief introduction to the background of the cryptogrammic chip design,and it clearly states the characteristic and the researching thoughts of cryptogrammic chip design with HDL.Then the design environment and cipher algorithms are introduced briefly. In this paper,the methodology and implementation with HDL of design based reconfigurable architecture are discussed in detail,which includes the implementations of algorithms circuit,register file with controllable node,decoder,interface and main controller.From the introduction of design process of every module circuit,we can see easily some general feature of VLSI design with HDL. methodology.Cryptogrammic chip introduced in this paper has been tested on the Altera's APEX20KE FPGA.The main clock frequency reached 40MHz.The chip includes 30,000 LEs.In order to utilize ESB resource in Altera's chip,we adopted embedded ROM and RAM and can realize the function of whole system with only one chip.lt is the embodiment of methodology and notion of SOPC(System On a Programmable Chip).The simulation of this cryptogrammic chip proves the correctness of function of the chip,which shows that the important ideology based reconfigurable architecture has special significance in designing of cryptogrammic chip.The design of this chip sticks to the general methodology of HDL design.lt is entered in HDL format with Innoveda's Visual HDL and simulated with Modelsim simulator,after synthesized with FPGA Compiler II ,the EDIF is entered in Quartus II ,which is supplied by Altera corporation to place and route.The sdo file produced by Quartus II is backannotated to the netlists and timing-simulation is been done.The success of this cryptogrammic chip also shows the effectiveness and advantage of the methodology of high level design with HDL.