Design Of General Purpose Microcontroller Based On RISC-V Architecture

With the continuation of the worldwide “core shortage” and the intensification of the Sino-US trade war,the independence of Microcontroller（MCU）,which is a basic chip product,is not only the premise of economic development but also a basic fuarantee for national security.In this context,this paper designs a microcontroller for low-power embedded scenarios based on RISC-V,the fifth-generation reduced instruction set architecture which is completely open source.This work firstly implements a MCU core that supports the RV32 IMC instruction set.This core bases on a two-stage variable-length pipeline,supports static branch prediction,and is equipped with independent high-performance multiplication and division modules.The processor bus interface adopts the AHB-Lite bus defined by ARM’s AMBA 5 bus protocol,which has better compatibility and scalability.What’s more,the processor also supports the debug mode defined by Si Five’s RISC-V debug spec 0.11 version,and can support system debugging and program downloading by cooperating with the debug module in the So C.On this basis,the author replaces the high-speed system bus of the Hummingbird E203 open source project with AHB-Lite bus.And then,implements a low-power MCU with the integration of the above So C and processor.After completing the micro-architecture design,the author also builts a test platform,and verifies the design’s compatibility of executing RISCV programs and handling interrupt and exception by running the "I","M","C" instruction set test programs officially provided by RISC-V and the Hello World program coded in C language.On the basis of software simulation,further tests and evaluates are executed through hardware implementation.First,test program in c language and benchmark programs are run on FPGA prototype.The design achieves a score of 1.46 DMIPS/MHz and 2.7 Core Mark/MHz,having the performance between ARM Cortex-M23 and ARM Cortex-M3.Finally,hardward synthesis based on SMIC’s 55 nm process is executed.Under the timing constraint of 200 MHz,the synthesized MCU core contains a total of 22949 cells with the total cell area of 50259.The average power consumption of running Dhrystone at 1.08 V is 2.8538 mW.