An Embedded SoC System Design Based On RISC-V Architecture

Integrated circuits are crucial to today’s rapidly growing Io T industry,and CPUs play a central role in integrated circuits.Different application scenarios have different performance requirements for CPUs.Currently,processors based on x86 architecture are not dominant in the embedded field due to increasingly complex instruction sets,high investment costs and high R&D difficulties.The processor based on ARM instruction set architecture,although occupying a large share of the embedded processor market,has high initial licensing fees and late royalties,and cannot be developed by users,making the development costs and cycles of individuals and organizations increase.The RISC-V instruction set architecture has been widely used in embedded SoC(System on Chip)design due to its completely free,simple architecture and self-customizable extended instruction set.However,domestic research has mostly focused on small-scale,low-power processors with two or three pipeline in performance evaluation.There are few studies on more advanced pipeline architectures and few studies on the RV32C compressed instruction set architecture for embedded applications.Firstly,this paper proposes a six-stage pipeline design scheme based on the traditional five-stage single-launch pipeline architecture,taking into account the static branch prediction mechanism of RISC-V and the balance of pipeline latency through an in-depth study of RISC-V instruction set architecture and pipeline architecture.This scheme adds one level of static prediction to the traditional five-level pipeline’s instruction-fetch stage,which means that the instruction-fetch stage is two levels and the other stages remain unchanged,thus increasing the processing speed of the pipeline in the prediction stage.On the basis of this six-stage pipeline architecture,clock beat analysis is performed for all instructions,and the module functions are divided and designed accordingly,and a processor based on RV32IMCZicsr instruction set architecture with AMBA AHB-Lite bus is finally implemented.The design is parametric and all instruction set architectures are configurable,and the RV32E instruction set can be implemented for embedded system applications.The processor architecture is equipped with PLIC(Platform-Level Interrupt Controller)and CLINT(Core Local Interruptor),which supports 40 interrupt sources with 7 priority levels.Based on the self-designed processor core,the APB bridge and the GPIO,USART,SPI,PWM and IWDG peripherals based on the AMBA APB bus are designed and completed independently to build an embedded SoC system.Second,the simulation test platform uses the RISC-V cross-compiler tool riscv-gnu-toolchain and C code for verification,writes relevant functional test C code,generates hex files with the cross-compiler tool,and parses the instruction code by Python script and loads it into ROM to simulate and test the processor core and peripheral modules,and verifies them with FPGA prototypes.Finally,through the DC synthesis tool developed by Synopsys,the logic synthesis of the RISC-V processor is completed based on the SMIC 0.18μm process library,with the synthesis target frequency at 50 MHz,and the performance parameters of the smallest processor core based on the RV32ECZicsr instruction set architecture are obtained with slack=6.99,and the synthesized core area is 219282.94μm~2,the gate level is about 7.6 k,and the power consumption is 142μW/MHz,which meets the design requirements.