An Accelerated SoC Design For Convolutional Based On RISC-V Processor

As Io T technology has been widely utilized in fields such as city,agriculture,industry and medical,a large number of Io T terminal devices have been manufactured and used.However,data collected by terminal devices may not always be transmitted to the cloud directly without any processing,especially video and image data.So processor can not processes increased number of data in time.Meanwhile unprocessed data lead to serious security problem and long-distance transmission leads to latency.Therefore,one major problem needed to be resolved in Io T technology is how to improve the data processing ability of terminal devices and extract feature data and recognition.This article,starting with multi-tasking and data processing,and combining requirements of terminal devices on low power,low resource and high performance,will discuss this problem in five aspects.(1)Related parameters on resources,power and performance of Ibex,CV32E40 P and CVA6 processors can be gotten by utilizing FPGA prototype verification.CV32E40 P has advantages on high performance,low power and low resources,and fulfill the requirements of terminal devices.(2)CV32E40P is embedded into CL multi-core architecture in PULP project and compile program to run the function modeling on the FPGA prototype.The result shows that multi-core architecture can run a single task or multiple tasks parallelly.(3)Full Crossbar bus architecture in AXI is replaced by semi Crossbar bus architecture.Consumed resources is lowered by 17.86% without affecting the transmitting speed.(4)Multipliers in Convolution Accelerator MAC unit is improved to higher the calculation efficiency and lower the consumed resource.Compared with the traditional shift multiplier,although it consumes 9% more resources,the performance is improved by 39.375%.(5)According to design ideology of modularization parallelism and pipeline,a convolution accelerator with six-stage pipeline is designed.In order to prevent traffic problem in data transmission,the computation speed is as high as 0.398GMAC/s,and 49.8% of multiplier performance is utilized,which is a decent performance compared with similar design.In all,this article proposed a Io T terminal devices,an SOC system with convolution acceleration design scheme,by researching on PULP platform provided by RISC-V.CV32E40 P fulfill all requirements on low power,low resources as well as high performance.Multi-core architecture improves multi-task processing abilities.Semi Crossbar bus architecture lower the unnecessary power consumed on bus.Improvement on convolution accelerator architecture provides high computation performance and pipeline design allow full play to MAC performance.