Design Of High-bandwidth Noise Shaping SAR ADC

Modern wireless communication maintains the demand for high bandwidth analog-to-digital converter(ADC).Successive approximation analog-to-digital converter(SAR ADC)is widely used in wireless communication because of its low power consumption and small area.However,its accuracy is limited to about 10 bits due to comparator noise and quantization noise.Noise shaping(NS)SAR ADC is a hybrid structure that introduces noise shaping technology into SAR ADC.Noise shaping can effectively suppress comparator noise and quantization noise and improve accuracy.However,due to the slow conversion speed of SAR ADC,the bandwidth of noise shaping SAR ADC is limited,so the high bandwidth noise shaping SAR ADC has become a research hotspot.In this thesis,a noise shaping SAR ADC with a bandwidth of 20 MHz and SNDR which is over 75 d B is designed for wireless communication applications.A second-order fully passive noise shaping circuit structure based on dual input comparator is proposed and passive signal residual summation is realized.The comparator adopts single input pair structure which has less input equivalent noise and offset than multi input pair comparator.The residual sampling capacitor is connected between the top plates of the capacitor array on both sides for residual sampling,which not only realizes twice the gain of the residual voltage,but also the residual sampling process has been completed at the end of the conversion,so there is no need to consume additional time for residual sampling.Using passive integration,the noise transfer function coefficient of the whole circuit is determined by the capacitance ratio,and the noise shaping effect has good stability.Based on the proposed second-order passive noise shaping circuit structure,a dual channel time interleaved second-order passive noise shaping SAR ADC combining coarse and fine ADC is designed.The dual channel is used to improve the ADC bandwidth.Combined with the sampling rate of 320MS/s,the oversampling ratio is 8,and since the number of channels is less than the oversampling ratio,the harmonics introduced by the mismatch between channels appear outside the bandwidth and do not need to be calibrated.Coarse ADC is used to quickly provide two channel with four most significant bit digital codes to improve the conversion speed,while single channel fine ADC converts the remaining eight bits to complete the whole conversion process.When designing fine ADC,two redundant bits are added to cover the mismatch between coarse and fine ADC.Based on TSMC 28 nm CMOS process,the schematic and layout are designed.The post simulation results show that under the conditions of 1V power supply voltage,320MS/s sampling rate and 3.125 MHz input sine wave signal frequency,the signal-to-noise distortion ratio of ADC reaches 80.41 d B,spurious free dynamic range 88.76 d Bc,bandwidth 20 MHz,power consumption 6.318 m W and overall Fo M value 175.4d B,which meets the index requirements.