Design Of High-speed And High-precision TI-NS-SAR Analog-to-digital Converter Suitable For IEEE 802.11 Ac/ax Standards

In recent years,with the rise of the Internet of Things,its demand for high-bandwidth wireless communication drives the rapid development of Wi-Fi.As an interface between analog and digital signals,the analog-to-digital converter is an essential part of Wi-Fi,and the SAR ADC has been widely used due to its advantages of high energy efficiency and simple structure.However,with the development of Wi-Fi,the low sampling rate and poor accuracy of SAR ADC under IEEE 802.11 ac/ax standards have become an obstacle to the development of Wi-Fi.Therefore,it is necessary to extend the advantages of SAR ADC to high sampling rate and high precision to meet the requirements of IEEE 802.11 ac/ax standards.In this paper,based on the requirements of IEEE 802.11 ac/ax standards for ADC,a hybrid ADC based on time interleaving(TI)-noise shaping(NS)-successive approximation register(SAR)structure was designed and implemented,which can push the harmonic distortion caused by interleaving out of the bandwidth.Compared with the traditional time interleaving ADC,the SNDR is improved effectively.In terms of the internal structure,in order to improve the accuracy of SAR ADC,a third order noise shaping circuit based on error feedback structure was designed.Compared with the traditional noise shaping structure based on cascade integrator feedforward,this structure has a higher matching degree with the SAR ADC capacitor array,so it can effectively reduce the harmonic caused by mismatch.At the same time,the noise transmission function of the structure produces a notch in the bandwidth,which further reduces the noise energy and improves the signal-to-noise ratio.In order to improve the sampling rate,a four-channel NS-SAR ADC time�interleaving structure was designed.While achieving time interleaving,in view of the characteristics of the SAR ADC's multiple clock cycles,a third-order midway feedback timing scheme was proposed,which maximizes timing overlap and significantly improves the conversion efficiency while achieving noise shaping.In this paper,the modeling of the system and the determination of system parameters are completed by MATLAB at first.Then,based on the TSMC 28nm CMOS process,the design of circuit,layout and post-simulation analysis are completed by using EDA platforms such as Virtuoso and Calibre.The results show that at the sampling rate of 320MS/s,the input frequency of sinusoidal signal is 4.95MHz,SNDR is 77.4d B,ENOB is 12.56bit,power consumption is 8.9m W,Fo M_S is 173.9d B,bandwidth is 40MHz,and the overall area is 0.12mm~2.It realizes the advantage extension of high sampling rate and high precision for SAR ADC,and meets the requirements of IEEE802.11 ac/ax standards for ADC.