Design Of A 12bit 500kS/s Low-voltage And Low-power SAR ADC

In many wireless sensor network applications,such as medical monitoring and mobile devices,it is essential to extend the lifetime of these systems and it is difficult to replace their batteries frequently.Therefore,low-power design is essential for analog-to-digital converter(ADC),a significant block in these systems.Successive approximation register analog-to-digital converter(SAR ADC)has simple structure,high energy efficiency and strong competitiveness in low-voltage and low-power design.A 12bit 500k S/s low-voltage and low-power SAR ADC is presented in this thesis,which is suitable for wireless sensor networks.Firstly,an energy-efficient switching algorithm based on semi-resting structure is proposed,the differential voltage variation on the top plates of capacitive digital-to-analog converter(DAC)is twice that of the general switching algorithm in each step,the top reference level of DAC will be reduced to half of the general if the input range is same.In the process,the"merge switch"is used frequently to passively generate the required third reference level,which further reduces the switching energy.When comparing the lowest bit value,the single-ended switching is only utilized,leading to 0.5LSB common-mode voltage variation.The proposed switching method achieves 99.22%switching energy saving and 75%capacitor area reduction compared with the conventional switching scheme.Based on the method,the ADC architecture is determined.The preamplifier of the dynamic comparator adopts a cascade dynamic bias structure.The dynamic bias structure can avoid the complete charge or discharge of the output nodes of the preamplifier and reduce the power consumption of the comparator without complex logic.The cascade structure is helpful to improve the gain and reduce the noise of the comparator.The sampling switch is a double-bootstrapped structure.Thus,Fairly small on-resistance is obtained,which maintains the accuracy and linearity of sampling.The layout is designed based on SMIC 180nm CMOS process in the paper.The core layout area of ADC is 755μm×555μm.When the supply voltage is 0.6V and the sampling rate is 500k S/s,the post simulation results show that the effective number of bits(ENOB)is11.44bit with a Nyquist-rate input,the signal-to-noise and distortion ratio(SNDR)is 70.63d B,the spurious-free dynamic range(SFDR)is 79.41d Bc,the power consumption is 1.96μW,and the Walden figure of merit(Fo M_W)is 1.41f J/conv-step.The design goals are realized.