The Study Of Novel SOI-LDMOS With High Breakdownvoltage

In recent years,high-voltage power semiconductor devices have been widely used in many areas such as smart home,rail transit and automotive electronics.The updating of high-voltage power semiconductor devices is faster and faster,and at the same time,the performance requirements for high-voltage power semiconductor devices are also higher and higher.The laterally double diffused metal oxide semiconductor(LDMOS)based on silicon-on-insulator(SOI)technology has the advantages of both SOI technology and LDMOS,including fast operation,low parasitic effect,simple fabrication,easy integration,and SOI LDMOS device can achieve ideal isolation.Therefore,SOI LDMOS is widely concerned in the field of high-voltage power semiconductor devices.From the point of device structure design,combining the lateral and vertical voltage mechanism,many high-voltage devices are studied,and then two new device structures are introduced in the paper.The first one is the SOI LDMOS device with hybrid partial buried P-type silicon layer(PBPL)and partial buried N-type silicon layer(PBNL).The device has two peaks in the lateral electric field distribution,which can better improve the RESURF effect,and provide enough adjustment space for the compromise between the drift region and the partial buried N-type silicon layer,thus the breakdown voltage(BV)of the device is increased and the on-resistance(Ron)is also reduced.The simulation results show that compared with conventional SOI LDMOS and buried N layer SOI LDMOS,the SOI LDMOS with hybrid PPPL and PBNL can achieve a higher breakdown voltage,and the on-resistance(ROn)is reduced by 26.5%and 24.6%,and its quality factor is the highest.The second one is the SOI LDMOS device with hybrid multiple partial buried layers(HMPBL SOI LDMOS),which is composed of a partial buried oxide,a partial buried P-type silicon layer and a partial buried N-type silicon layer.The multiple partial buried layers can increase the breakdown voltage and reduce the on-resistance of the device.The simulation results show that compared with the SOI LDMOS with buried N layer and the SOI LDMOS with buried oxide double-step,HMPBL SOI LDMOS can achieve a higher breakdown voltage,and the on-resistance is reduced by 11.9%and 9.7%,respectively.Although compared with the SOI LDMOS with hybrid PBPL and PBNL,HMPBL SOI LDMOS achieves a slightly larger on-resistance,but its breakdown voltage is increased by 11%,hence it still has a higher quality factor(Figure-of-merit,FOM,=BV2/Ron).