Research On Models And Characteristics For The Thin Layer SOI High Voltage LDMOS Devices

SOI(Silicon on Insulator) high voltage LDMOS(Lateral Double-diffused Metal Oxide Semicondutor) devices are widely used in smart power integrated circuits such as automotive electronics, medical electronics, smart appliance and aerospace. Compared with thick layer SOI LDMOS, thin layer SOI LDMOS provides good technology compatibility and less parasitic effects. Hence, thin layer SOI high voltage LDMOS devices have good prospects in power integrated circuits,expecially in power switching and driver. However, due to back gate bias, characteristics for the thin layer SOI P type high voltage LDMOS devices have been affected. Compared with the N type, RESURF(REduced SURface Field) is inhibited for SOI P type high voltage lateral devices, leading to a low breakdown voltage. Meanwhile, due to limited electric field in dielectric layer, breakdown voltage for thin layer SOI high voltage LDMOS devices is difficult to exceed 600 V, which hinders the application in integrated circuits with higher supply voltage. At present, the researches over the world focus on thick layer SOI high voltage LDMOS with exceeded 3-μm-thick SOI layer, and less care has been devoted to thin layer SOI LDMOS, of which the thickness of SOI layer is less than 1.5 μm, especially PLDMOS. In addition, most reported breakdown models are based on thick layer SOI LDMOS, but the thin layer one.Based on electric field modulation approach, back gate effect and block characteristics for thin layer SOI high voltage LDMOS are investigated. Back gate breakdown model and ultra thin layer SOI high voltage VLD LDMOS breakdown model are developed, and two type of novel device structures are proposed.Main works are list as below:1. Back gate breakdown model.Based on the intrinsic back gate effect for SOI PLDMOS, back gate breakdown model is proposed, which gives a criterion for back gate puch-through breakdown. The back gate breakdown voltage model reveals up the back gate punch-through breakdown mechanism for thin layer SOI PLDMOS, and obtains the dependence of back gate voltage on the impurity concentration of nwell and the junction depth of pf region. As the criterion is satisfied, back gate punch-through breakdown occurs. The proposed model can be applied to all SOI PLDMOS. Meanwhile, based on the model, the breakdown characteristic of SOI PLDMOS with 1.5-μm-thick SOI layer is investigated. The structure parameters are optimized to avoid punch-through breakdown. Experimental results show the breakdown voltage of the thin layer SOI PLDMOS reach 329 V with back gate voltage of-200 V.2. Breakdown model for ultra thin layer SOI high voltage VLD LDMOS.Breakdown voltage model for ultra thin layer SOI high voltage VLD LDMOS is proposed, which gives the RESURF condition. Based on enhanced dielectric field theory, ultra thin drift region is adopted to enhance critical breakdown electric field of silicon, resulting in a high breakdown voltage. Based on the RESUFR condition, the characteristics of breakdown voltage and specific on-resistance are investigated. Experimental results show that the breakdown voltage and specific on-resistance are 644 V and 24.1 Ω·mm2, respectively, for ultra thin layer SOI high voltage VLD LDMOS with 0.15-μm-thick SOI layer.3. Two type of novle device structures.Based on above vertical breakdown mechanism for SOI high voltage devices, two type device structures are proposed. The first type device is developed from the concept that improving vertical breakdown voltage, contains: T-RESURF SON LDMOS、PSUB SOI VLD LDMOS and SOI LDMOS with interface charge. Compared with conventional SON structure, specific on-resistance for T-RESURF SON LDMOS reduces by 40.8% which maintaining the same breakdown voltage. The second type device is SOI MOSFET with U type trench gate, developed from the concept of accumulation conduction. Compared with conventional SOI with trench gate, the specific on-resistance of SOI MOSFET with U type trench gate reduces by 83%, breaking silicon limit.