Design Of 100V Shallow Trench Isolation SOI-LDMOS

100V Lateral Double-diffused Metal Oxide Semiconductor(LDMOS)has been widely used in automotive electronics and smart medical fields.The aforementioned application scenarios require LDMOS devices to have both high performance and high reliability.Traditional silicon-based LDMOS is difficult to meet the requirements of low on-resistance,high breakdown voltage and high reliability due to the"silicon limit"problem,while LDMOS devices using silicon on insulator(SOI)technology can make it.SOI technology can alleviate the contradictory relationship between on-resistance and breakdown voltage characteristics and improves device reliability.Therefore,it is of great significance to study 100V SOI-LDMOS devices.A new type of 100V shallow trench isolation SOI-LDMOS device with P-type buried layer has been proposed by this thesis.First,the device improves the lateral surface charge effect of the device by adding a shallow trench in the SOI layer,thereby improving the lateral breakdown voltage of the device;adding P-typed layer between the SOI layer and the buried oxide layer to enhance the RESURF effect of the substrate and improve the vertical breakdown voltage.The auxiliary depletion effect of the P-type layer on the drift region can increase the doping concentration of the drift region,thereby achieving extremely low on-resistance.Compared with SOI-LDMOS devices of the same specification,the breakdown voltage of shallow trench isolation SOI-LDMOS devices with P-type buried layers has been increased from 125V to 152V,an increase of 22%,and the on-resistance has been reduced from 140m?·mm2 to 125.8m?·mm2,a reduction of 11%.In addition,this thesis also studied the reliability of SOI-LDMOS devices.The study found that when the working voltage is high,the serious Kirk effect is the cause of the low on-state breakdown voltage.Setting an N-type buffer on the drain can effectively expand the safe working area and improve the electrostatic discharge protection capability;the interface state generated by the hot carrier injection at the corner of the shallow groove bottom will cause serious on-resistance degradation,improving the bending of the groove bottom angle and appropriately reducing the length of the shallow groove can reduce the impact ionization strength,thereby improving the hot carrier reliability of the device.The threshold voltage of the designed device is 1.42V,the off-state breakdown voltage is 152V,the characteristic on-resistance is 125.8 m?·mm²,and the off-state leakage current is 1.3?10^-14 A/?m,the open-state breakdown voltage reaches 112V,the peak value of impact ionization under the worst stress state is 2.97?10²⁸cm^-3/s,and the return point voltage under the pulse condition of the transmission line is 202V,and the secondary breakdown current is 6?10^-3A/?m,which satisfies the design index and the application requirements of LDMOS devices in the fields of automotive electronics and intelligent medicine.