Research And Implement On LDPC Encoder And Decoder For 5G Communication System

The 5G has been developed to meet the new requirements of people such as low latency,high reliability and large-scale device connectivity in the internet-of-things era.Since the Turbo code widely used in 4G can no longer meet the requirements of complexity,flexibility and latency in 5G,the Low-Density Parity-Check（LDPC）code is finally identified as the data channel coding scheme for the Enhanced Mobile Broad Band（e MBB）scenario in the 2016 RAN1#86bis meeting.With the coding scheme determined,the study of the encoding and decoding algorithms and related hardware implementation for 5G LDPC codes has recently become a research highlight in the world.Research in this thesis focuses on the hardware implementation and optimization of LDPC encoding and decoding algorithms in 5G based on the Field-Programmable Gate Array（FPGA）.The encoder in this thesis utilizes the special double diagonal structure and the identity submatrix in the check matrix of 5G LDPC code on the one hand to reduce hardware resource consumption.On the other hand,the latency of calculating parity bits is reduced by parallelizing the operation process of intermediate results as much as possible with the parallel structure in encoder,while flexible structure allows this encoder to compatible with various code-lengths and code-rates in5G.In terms of LDPC decoder,this thesis mainly focuses on how to reduce the complexity and improve hardware resource utilization.The proposed decoder is implemented with the Layered Min-Sum Algorithm（LMSA）to reduce the consumption of logic resources and the maximum value of the expansion factorZ_max in 5G standard to have inter-standard flexibility,which is decided through the comparison result of different decoding algori thms and hardware structures.However,the decoders designed withZ_max will result in a great many hardware resources in idle state and lead to low hardware utilization when the current expansion factorZ≤Z_max/2.A novel low-complexity check node unit is proposed to solve this problem and enhance the decoding speed at the same time,which organizes idling comparers in groups to assist the update progress of a check node originally processed by one comparator in LMSA whenZ≤Z_max/2.In addition,a novel message compression method is utilized when storing the messages from the check node to the variable node and some low complexity comparers are employed to further reduce the consumption of memory and logic resources.