FPGA Implementation Of High Speed Encoder And Decoder For LDPC

Stratospheric high-altitude relay platform for high-speed data transmission requires efficient error-correcting code technology to guarantee their communications reliability. The Quasi-Cyclic (Quasi-Cyclic. QC) LDPC code can achieve linear time encoding, and it has efficient decoding algorithm, which is suitable for the implementation of the hardware design. This thesis aims at the implementation of155.52Mbps LDPC encoder and decoder, and the main works consist of the following aspecets:1. Based on the introduction of the principles of LDPC codes, the calculations of generation matrix and the iterative decoding algorithm in BP are discussed. The simulation result of the (8176,7154) code-based QC-LDPC code is presented.2. According to the structure of the generation matrix, the FPGA design and verification of the QC-LDPC encoder with a speed of155.52Mbps is conducted. Based on the quantization of the decoding algorithm, the FPGA implementation of a partly-parallel QC-LDPC decoder with a high decoding throughout rate of155.52Mbps is given.3. A feasible base-band scheme for the hardware platform is presented and the proper devices are selected to complete the design of the circuit board. A test scheme of the encoder and decoder is particularly given; the test results of the encoder and decoder are also presented.