Design And Implementation Of Non-binary LDPC Encoder And Decoder

Channel coding is an essential technology for reliable communication over noisy channels.The performance of LDPC(Low-density Parity-check)codes can approach the Shannon limit,so LDPC codes have been extensively studied and applied.Recently,it has been proved that LDPC codes over GF(q)can offer better error-correcting performance than their binary counterparts.We studied deeply into the method of encoder and decoder implementation of LDPC codes based on FPGA.The paper's main work includes: studying principle of encoding and decoding algorithm of LDPC codes over GF(q),using MATLAB simulation software to compare with the simulation result of a variety of encoding and decoding algorithm,and finally finishing the FPGA implementation of LDPC codes over GF(q)encoder and decoder.Firstly,we introduced the basic concept and study domestic and overseas of LDPC codes,then the representation method,which led to a kind of special type of LDPC codes--Nonbinary Quasi-Cyclic LDPC codes.Nonbinary QC-LDPC codes could keep channel performance in the same status and reduce greatly the encoding complexity.That was why it has a high application value.Secondly,we systematically analyzed and summarized the method of encoding and decoding algorithm of LDPC codes,compared the merits of the traditional encoding algorithm and fast encoding algorithm,and deduced the BP decoding algorithm of message update rules in white gaussian noise channel,as well as the evolving FFT-BP decoding algorithm and the extended min-sum decoding algorithm.Through comprehensive analysis of choosing the fast coding algorithm and the extended min-sum decoding algorithm for LDPC codes over GF(q)of the basic design thought for the encoder and decoder.Finally,based on fast coding algorithm,the study chose check matrix based on LDPC codes over GF(8),designed a kind of low storage and efficient LDPC codes encoder,which could only store each child-matrix's first address,and through positive and reverse order,calculated the check digits.This method could improve the encoding speed and save FPGA logic resources overhead.Decoder was designed according to the extended min-sum decoding algorithm,variable units and check units update adopted parallel between block,while updating in a serial manner in each block.The method could effectively reduce the decoder for hardware storage space utilization,and reduce the complexity of decoding circuit wiring.