Study On Efficient Implementation Of LDPC Encoder And Decoder

With the rapid development of Very Large Scale Integration （VLSI） techniques andthe renaissance of modern coding theory, based on near-Shannon limit error correctionperformance, low complexity decoding algorithm, and high parallelism hardwareimplementation architecture, LDPC code has attracted tremendous attention in academiaof the channel coding area. Recently effective implement technology of LDPC encoderand decoder has gradually focused by researchers. This dissertation is intended toinvestigate the effective implement technology of LDPC encoder and decoder. The mainresults are summarized as follows: high-throughput implementation of LDPC encoders,low storage high-speed implementation of LDPC decoders, Joint design of LDPCencoder and decoder, and dynamic schedule for layered decoding of LDPC codes.Firstly, we present a high-throughput encoding method for IEEE802.16e-likeLow-Density Parity-Check （LDPC） codes. It is based on a fast double-recursionpipeline method, and can significantly improve the encoding speed. For more parallelismand less storage consumption, a partially-parallel architecture is designed. Furthermore,the storage system is optimized for parallel multi-frame coding, and the data storage unitand RAM address generator are shared for improving resource utilization.Secondly, an efficient storage method of hard decisions sharing intrinsic and extrinsicmemory banks for partially parallel QC-LDPC decoder is proposed. Extra memory banksfor storing hard decisions are avoided in our method, which result in significantlyreduced consumption of routing complexity. In addition, by analyzing the loop iterationsof the LDPC decoding process, a variable node processing unit and check nodeprocessing unit completely parallel alternate processing two data frames structure isgiven, on the basis of the structure a dynamic address access management is proposed,Using these design the decoding throughput can be improved about one times but notincrease the FPGA resource requirement. In view of the traditional iterative number fixeddecoder design, this paper also presents a number of iterations variable LDPC codedecoder design method, which can reduce the total clock cycle of the decoder, verysuitable for real-time decoder implementation.Thirdly, by analyzing the commonality of the encoding and decoding process of LDPCcodes, a joint design of FPGA-based encoder and decoder of LDPC codes is proposed,the design can effectively reduce the system of hardware resource consumption withoutsacrificing the throughput.Finally, according to the syndrome of check nodes is zero or not and the adjacency relation between nodes design of a node reliability metrics, a low complexity efficientdynamic schedule for column layered decoding of LDPC codes is proposed, it tackles theconventional high computational complexity logarithmic likelihood ratio （LLR） metricmethod to measure the reliability of nodes, analysis and simulate results show that theproposed algorithm achieved good performance, at the same time its complexity is muchlower than other LDPC decoding algorithm.