The Design Of Efficient LDPC Codes Encoder And Decoder Based On FPGA

With the rapid development of modern digital communication systems, Low Density Parity Check codes, also known as LDPC codes, has become an important part in the area of error correction coding technology thanks to its approaching Shannon limit of high performance, low complexity of decoding algorithm and high level parallelism architecture on hardware implementation in the recent years. This paper studies deeply into the method of efficient and low storage encoder and decoder implementation of LDPC code based on FPGA. The paper’s main work includes: studying principle of encoding and decoding algorithm of LDPC codes, using Matlab simulation software to complete the check matrix structuring, comparing with the simulation result of a variety of encoding decoding algorithm, and finally finishing the FPGA implementation of efficient and low storage LDPC code encoder and decoder.Firstly, this paper introduced the basic concept and study domestic and overseas of LDPC code, then the classification and representation method, which led to a kind of special type of LDPC codes-- quasi-cyclic low density parity check code. QC- LDPC code combined structural and random characteristics, which could keep channel performance in the same status and reduce greatly the encoding complexity. That was why it could be widely used in many digital communication system.Secondly, based on Matlab simulation, the paper realized the different construction method of LDPC code check matrix. After a series of simulation test, the advantages and disadvantages of each form of construction has been analyzed.Then, the paper systematically analyzed and summarized method of LDPC encoding and decoding, compared the merits of the traditional decoding algorithm and fast decoding algorithm, and deduced the belief propagation decoding algorithm of message update rules in white gaussian noise channel, as well as evolving log likelihood ratio decoding algorithm and the mini-sum decoding algorithm. Through comprehensive analysis of choosing the fast coding algorithm and the mini-sum decoding algorithm for efficient LDPC codes of basic design thought for the decoder.Finally, based on fast coding algorithm, the study chose check matrix based on the IEEE 802.16 e standard, designed a kind of low storage and efficient LDPC codes encoder, which could only store each child-matrix’s first address, and through positive and reverse order, calculated the check digits. This method could save FPGA logic resources overhead and improve the encoding speed. Decoder was designed according to the mini-sum decoding algorithm, variable units and check units update adopted parallel between block, while updating in a serial manner in each block. The method could effectively reduce the decoder for hardware storage space utilization, and reduce the complexity of decoding circuit wiring.