Research And Design Of Low Jitter Phase_locked Loop For High Speed LVDS Interface

With the development of information technology, due to the remarkable demand of high speed data acquisition and transmission in the applications including wideband communication, industrial control, measuring equipment, medical instrument and military radar, the interface technology of high speed serial signal transmission in the basis of LVDS(Low voltage differential signal) become a focus in the microelectronics science. As the PLL(Phase Lock Loop)is an important module of the LVDS interface system, the output noise will reduce the system performance. This paper researches the approach to reduce the phase noise of the PLL in the LVDS high speed interface system, the main work of the paper includes:A system level methodology to reduce the phase noise is proposed in the basis of analysis of the internal noise of the PLL. The input noise to output transmission function is derived and the effect of every input noise on the whole system noise is analyzed, targeted to obtain the effect of loop parameters on the output noise and the methodology to reduce the noise depending on loop parameters optimization.A circuit level methodology to reduce the noise is proposed in the basis of analysis on each module. A new structure of the phase frequency detector is adopted to solve the problem of Dead Zone. The bootstrap charge pump with the unit gain amplifier is adopted to reduce voltage ripple caused by charge sharing. The current source is cascade to improve the match. The conduction time is 632 ps and the phase noise is-234.9dBc/Hz@1MHz, which proves that the purpose of clock jitter reduction is achieved. Dual control path is used in the filter to achieve the purpose of in-band noise cancellation, which reduce the gain of VCO to a third of single control path and guarantee the regulation range.The layout design to reduce the noise and the post-simulation were completed. The circuit in SMIC 0.18μm CMOS Mixed-signal 1P4 M process occupied 700μm*320μm, which uses the signal flow placement and routing methodology to reduce the non- ideal factor effect. The post layout result shows that the lock time is less than 5us, the phase noise is-102dBc/Hz@1MHz and the total current is 5mA, when the input signal frequency is 25 MHz and output frequency is 1.6GHz.The paper presents a PLL with a high lock speed and low phase noise which can satisfy the requirement of the LVDS interface circuit clock and other specifications. The proposed design methodology provides a reference for low noise PLL design.