Design Of Low Cost 4*25G Multi-channel Parallel Bit Error Rate Tester

In modern information exploding society,the rate of communication system is constantly increasing to meet the increasing capacity demand.Ethernet with typical rate of40 Gbps or 100 Gbps is the key technology to be developed.At the same time,it is necessary to ensure the reliability of data transmission at such high transmission rate.It is of important value to develop a bit error ratio tester(Bert)which is matched with the optical module or optical system.Based on the investigation of the background of this kind of instrument at home and abroad,a low cost,high-speed Bert with 25 G bps single channel rate is designed in this thesis.This Bert can support a variety of output pseudorandom code type with flip.4 channel parallel test is also satisfied.The Bert is mainly designed for 100 Gbps optical module or optical system,which can provide convenience for a large number of bit error ratio tests.Specific research content:(1)According to the basic research situation at home and abroad as well as and the error test principle,the chip module selection is identified,and the optimal system design scheme is selected.(2)Principle chart and high speed PCB Layout are designed.STM32F103RBT6 are introduced in detail as the main controller.The hardware principles of 4 channel parallel high-speed bit error ratio tester based on chip IN012525-CQ are also studied.Besides,the thesis focuses on the problem of high speed signal integrity.(3)The corresponding lower computer control program is designed.The bit error count and bit error rate functions are realized.Design of human computer interaction program based on touch screen is completed.(4)The performance at both the transmitter and the receiver of high-speed Bert are tested,including the signal eye testing at the transmitter,the receiver connectivity test and sensitivity conformance test.The reliability of the Bert is verified and system indexes are evaluated.