Architecture Design Of Multi-rate LDPC Codec

With the development of communication technology,channel coding technology has become a vital part of communication transmission.In the forward error correction(FEC)technology,redundant data is added according to a certain algorithm,which enables the receiver to reconstruct the erroneous data.As a forward error correction code approaching Shannon’s limit,low density parity check(LDPC)code has excellent error correction performance,which is widely used in a variety of communication protocols,such as the IEEE 802.11 n standard,Digital Video Broadcasting-Satellite-Second Generation(DVB-S2)standard,Consultative Committee for Space Data Systems(CCSDS)standard and5 G New Radio(NR)standard,etc.However,in the applications of high code rate and large code length,the LDPC codec architectures have high resource utilization and throughput loss.In some rate adaptation algorithms,the throughput of the LDPC codec is severely degraded,especially at low rate.This article focuses on the problems of high resource utilization and serious throughput attenuation at low code rates in the LDPC codec architecture based on the CCSDS near-Earth standard.The main work includes the following two aspects:Firstly,the special structure of C2 code and the structural characteristics of quasi-cyclic LDPC(QC-LDPC)code are studied in the CCSDS near-Earth standard,and the problem of high resource utilization is analyzed in encoder architecture with large code length.A pre-processing method called register configuration is developed in this thesis,which effectively reduces the logic resources of the control unit.According to the special similarity between the first-row vectors in the C2 code,a search algorithm with similar structure is adopted,which effectively integrates similar computing units.A novel architecture with low resource utilization is proposed,which utilizes the structural characteristics of the quasi-circulant matrix.By dividing the input bit vector into blocks,the bit vectors of all blocks are processed with the inherent parallelism of the quasi-cyclic matrix at the same time.The calculation circuit of each check node is optimized by the search algorithm based on the similar structure,the similar circuit structure is integrated through the two-layer architecture,which further reduces the logic resources.The proposed architecture achieves a throughput of 4.69 Gbps using only 1658 LUTs and 1038 Flip-Flops.Then,aiming at the rapid throughput attenuation of the codec architecture with variable rate at low code rates,this thesis adopts a shortening technology that uses block length as the minimum unit,which is effectively combined with the encoding and decoding algorithm.In the proposed encoder architecture,the encoding period is dynamically adjusted by introducing block tags.For the bit flipping(BF)algorithm with slower convergence,an optimization algorithm is proposed so that check node process unit no longer participates in the iteration.Based on the proposed single-bit decoding algorithm,a single-check node process unit multi-variable node process unit decoder architecture is proposed.Through block early termination and iteration early termination,the decoding cycle is effectively shortened.The proposed codec architecture is matched,which adopts the C2 code and supports 14 code rates.Compared with other codec architectures,the proposed codec architecture has a lower throughput loss in the available code rate,which has a higher throughput at low code rate.