Design And Realization Of Multi-standard LDPC Decoder Based On RS-TPMP

LDPC, known as Low Density Parity Code, excels in approaching the coding performance of Shannon Limit among existing coding methods. As for decoding performance, LDPC characterizes relatively simpler decoding algorithm, reducing its failure rate in checking error code words to almost zero. The above strengths enable LDPC to enjoy wide application in all fields of modern communications standard with exceptionally high practical value.The diversity of communications channel requires diversified correcting ability in different channel environments. Therefore, research on flexible error correction codes technology with variable bit rate or code length is in urgent need. As data size of modern communications system grows increasingly enormous, boosting data throughput rate to ensure instantaneity and improve system efficiency has become one of the inalienable hot issues in the research of LDPC decoder.There are numerous methods to boost data throughput rate of LDPC decoder. Traditional LDPC decoders employ parallel or semi-parallel method, and basically all concentrate on single code rate standard. Parallel LDPC decoder fails in the structure design of multi-standard, code rate variable hardware as the realization of hardware becomes growingly complex. Semi-parallel LDPC decoder is unable to ensure parallel compatibility due to its lack of flexibility in hardware structure, and has certain trouble in boosting throughput rate. The multi-standard LDPC decoder studied in this paper, on the basis of RS-TPMP schedule algorithm, the application of decoder hardware circuit designed in this paper is able to meet requirements of BER performance and throughput rate of multi-standard LDPC decoder. Main research contents of this paper are as follows:(1) The paper designs the procedures of RS-TPMP schedule algorithm and TDMP schedule algorithm, computes and compares the throughput rates of the two algorithms during hardware implementation.(2) The paper, with reference to general frame of multi-standard LDPC decoder, makes deliberately designs and analyses the working flow chart of hardware system of multi-standard LDPC decoder. In combination with the integral timing design and decoder system state machine design of Pipeline, this paper effectively addresses conflicts between the timing of input initialization and the timing of code data processing.(3) The paper makes theoretical research into matrix transformation principle of LDPC decoder and analyses data storage of decoder variable node, realizing the semi-parallel operation of decoder. The design of advance iteration timing guarantees that row data update of decoder synchronizes with decision module, boosting its throughput rate.(4) This paper designs the data processing module, circulation unit, minimum value search unit module, ROM and code output module of decoder, realizing the compatibility with multi-standard bit rate.(5) This paper attempts to print part of the node data on C-emulation platform and establish RTL testing platform, with the purpose of achieving conformity of the two platforms, which ultimately reaches the target of correct decoding output of decoder with assistance of Debussy tool in wave verification.