Optimal And Design Of LDPC Codec With Multi Code Length And Rate Compatibility

Low-Density Parity-Check(LDPC)is one of the best performance error correction codes at present.Its performance is close to the Shannon limit.It is currently widely used in data storage and various communication standards.In the 3GPP conference held in 2016,the LDPC code was determined as the coding scheme for enhanced mobile broadband(e MBB)in 5G communications.With the development of 5G communication technology,smart home and Internet of Things technologies will be widely used,which will be the main application scenario of m MTC business in the future 5G communication.In order to meet the application requirements in different scenarios,the coding method is required to be flexible and changeable,and compatible with multiple code length code rates.In response to this problem,the paper combines LDPC codes with multi-code length code rate-compatible codec algorithms and check matrices.The structure is researched deeply,and the LDPC codec suitable for multi-code length code rate compatibility is implemented based on the FPGA platform design.The main content of the paper is as follows:First,the paper analyzes the current application status of LDPC codes and code rate compatibility,conducts an in-depth analysis of the check matrix structure of LDPC codes,constructs a check matrix with excellent performance based on the 5G standard matrix structure,and combines multi-code design to achieve compatible multi-code Long code rate check matrix;in order to facilitate hardware implementation,in combination with QC-LDPC fast iterative coding algorithm,the encoder is designed with a semi-parallel coding scheme;in the aspect of decoding algorithm research,the layered decoding algorithm is carried out In-depth research and improvement and optimization of the selection of layered parameters can effectively reduce the resource occupation of multi-code-length-compatible decoders while ensuring decoding performance.Then,a software simulation analysis is performed on the determined check matrix,coding / decoding algorithm and related parameters to verify the performance of the check matrix and coding / decoding algorithm,and at the same time determine the parameters used by the hardware implementation.Then,the multi-code long code rate compatible codec design is completed on the FPGA platform through Verilog language,and the timing simulation analysis is performed by Modelsim to verify the functional effectiveness of the designed codec.Finally,the encoder and decoder are individually packaged with IP cores through Vivado,and system debugging and verification are completed on the Xilinx KC705 hardware development platform.After system debugging and verification,the multi-code long code rate compatible LDPC codec designed in this paper can effectively reduce the resources consumed by hardware implementation while improving the decoding performance,which has good theoretical and engineering application value.