Design And Implementation Of Codec Chip Based On QC-LDPC Variable Code Length And Code Rate

LDPC(Low Density Parity Check Code)is a group error correction code with a sparse parity check matrix,which has the performance of approaching the Shannon limit,is simple to describe and implement,and is easy to perform theoretical analysis and research.Decoding is simple and can implement parallel operations,suitable for hardware implementation,etc.LDPC have become one of the research hotspots in the field of channel coding and decoding with its excellent performance,concise form,and good application prospects,and has been widely promoted in various communication standards.In this thesis,we mainly research the encoding and decoding algorithms of LDPC code,and describe the chip design scheme and implementation scheme based on quasi-cyclic LDPC code encoding and decoding technology.Firstly,the theory of channel coding and LDPC and the current development status of LDPC are introduced.This thesis discusses and researches from LDPC code construction method and coding algorithm,and introduces two kinds of construction methods and coding technology of LDPC code.Through the study of four common decoding algorithms,simulation comparisons of decoding algorithms are performed.Because the improved minimum sum algorithm is well suited for hardware implementation,the variable length code decoding algorithm of this subject is based on an improved minimum sum algorithm.Secondly,the LDPC code performance analysis and optimization design technology are researched,including the density evolution theory optimization design technology,external information transfer graph analysis and design technology,Gaussian approximation analysis design technology.Then analysis was performed on the cyclic LDPC code construction technique.Combining the random method and the algebraic method to construct an effective LDPC code H-matrix is the key point and difficulty of constructing the quasi-cyclic LDPC code in this thesis.According to the characteristics of quasi-cyclic coding technology,the design scheme of serial or parallel quasi-cyclic LDPC code coder module based on shift register accumulator circuit is proposed.The key points of decoding algorithm design are presented by analyzing and comparing the decoding method of cyclic LDPC code.It is improved by considering the fact that Log-BP decoding algorithm is more practical and easier to implement.Through the analysis of resource consumption,the number of iterations and the realization of the quantized bit hardware are considered,and the decoding module design is implemented in parallel.Finally,in order to reduce the interface requirements for board-level signals and improve the reliability of the system,the design of the chip phase-locked loop is researched emphatically.For a wide range of miniaturized systems,the chip low-power design techniques were analyzed.In addition,the chip's testability and test platform were designed.After the power network design and signal integrity analysis,the physical layout design was completed.