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Design And Implementation Of The High Speed LDPC Codec For 802.11ad

Posted on:2016-03-22Degree:MasterType:Thesis
Country:ChinaCandidate:J XiangFull Text:PDF
GTID:2308330473454433Subject:Communication and Information System
Abstract/Summary:PDF Full Text Request
LDPCcode, which first proposed by Dr.Gallagerin the1960 sin his doctoral thesis,is a graduallinear blockcode of which performance is close to the Shannon limit. Since then it has been neglected due to lack of computing power and storage capacityand the shortage of visible and efficient decoding algorithm which severely limit its development.It did not arise any attention until Tanner proposed representation of graph theory of LDPC code in 1981, which is now known as the Tanner graph and it performs the characteristics and decoding of LDPC code more intuitively. In 1999 MacKay rediscovered the LDPC code and proposed LDPC decoding algorithmswith good performance and easy implementation which made the academia realizedpotential of Gallager’s previousresearch.MacKay and Neal proved the performance of LDPC codes is close to the limit of channel capacityand it has linear complexity. Afterwards, research related algorithms of LDPC codes with high performance back to the forefront of scientific research again. With the further development of LDPC codes, technology related has already become refined which gradually promotes the process of practical use in business application industry and it is also placed in the standardsof CCSDS and other wireless communication systems.Under the super broadband requirements of modern communication systems, BP and LLR BP decoding algorithmsof LDPC code, sum and product decoding algorithm and other traditional algorithms are difficult to meet the high-speed implementation of VLSI arithmetic decoding. After 2000, with the development of probability calculation, an efficient algorithm different from the traditional decoding algorithm was proposed, which is LDPC decoding algorithmbased on the calculation of the probability. The core idea of this algorithm is to change the traditional characterizing way of binary values domain and using bitstream to represent probability value, this changed the traditional structure of arithmetic unit and making the implementation of hardware structure of probability calculation easier compared to traditional. For example, the probability calculation of multiplication can be achieved only by an AND gate operation, the structure can be greatly scaled Oddo muxes function of the hardware is easy to achieve in order to shorten the critical path and reduce power consumption guarantee. In addition, the weight of each bit heavy bitstream same probability, which means that the probability is calculated to achieve is an element algorithm, LDPC decoding algorithm to calculate the probability of decoding algorithm is better than the traditional fault-tolerant features. This paper is to study the probability calculation based on a high-speed multi-rate LDPC encoding and decoding system FPGA, the main work and innovations are as follows:1. In this thesis, coding and decoding system based on parallel processing architecture is applied. The coding system is consists of two independent coder components while the decoding system is comprised by four independent decoder components in which two independent components compose ping pong structure.2. The structure with a variable degree of nodes makes the decoding system can choose a variety of bit-rate coding.3. Optimize decoding structure which makes the decoding time is shortened with the bottleneck of the system to meet throughput requirements.4. Complete the simulation and implementation of hardware and software systems, which improve the BER performance baseband transmission system and the project quality HD video playback.
Keywords/Search Tags:LDPC code, digital signal processing, stochastic method, multiple bit rate
PDF Full Text Request
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