Designand Implementation Of The High Speed LDPC Codec

LDPC code is a linear blockcode, which is completely determined bythe parity check matrix. The LDPC codewasproposed by Gallager in his doctoral dissertation in the last century 60’s. The LDPC code is ignored for a long time due to its implementation complexity. In 1981, Tanner was proposedfor LDPC codegraph representationmethod,which is known astheTannergraph. LDPC code retracted theattention of researchers. In 1995, MacKayand Neal proposed a novel LDPC decoding algorithm,which provided a good performance andefficient implementation scheme for LDPC codes. Now,the technologies, which related with LDPC coding and decoding algorithms, have significant improvements and are widely applied in communications systems.With the rapid developmentof future wide band communication systems, traditional LDPC decoding algorithms, includingBP, LLR and SPA, cannot tomeetthroughput requirements with thevery largesizeintegrated circuit(VLSI) operationalimplementationtechnology. Therefore, it is necessary that new VLSI implement scheme should be provided for the traditionaldecoding algorithm with high efficiency.It is also the motivation of stochastic computation applied for LDPC decoding in this thesis. The core idea of the stochastic computation based LDPC decoding algorithm is to represent probability values with stochastic bit streams, which can perform the complex probability arithmetic with simple bitwise operations. One obvious advantage of stochastic computation is that the hardware implementation of stochastic arithmetic is much simpler than traditional radix arithmetic. For example, multiplication can be performed with an AND gate, while scaling addition is performed with a multiplexer. The simplicity of hardware also brings short critical path and energysaving. Moreover, all the bits in the stochastic stream have the same significance. It means that stochastic arithmetic has better fault tolerance than traditional radix arithmetic. In this thesis, the FPGArealizationscheme for multirate LDPCdecoder is provided,and the theoreticaldeduction with experimental analysisfor stochastic computation based LDPC decoding algorithm is studied.The main work and innovations of this thesis are listed as following:1. Design LDPCcoderand testplatform,including the hardwarestructure design for the multiple rate LDPCcoder and its realization on FPGA platform.2. Research on serial correlation for stochastic computation, the performance analysis for the decoding algorithm is provided.3.Realize the multiple rate LDPC decoder with stochastic computation on FPGA platform.