Research On The LDPC Compilation Code Algorithm For 5G-NR And Its FPGA Implementation

Channel coding technology is the key to ensuring high-speed and high-quality transmission of 5G mobile communications.The Low Density Parity Check(LDPC)code was selected as the coding scheme for the data channel in the enhanced Mobile Broadband scenario of the5 G system in 2016.Faced with the requirements of the diversity of 5G communication scenarios and high-speed transmission,it is particularly important to design a codec with high throughput and compatibility with multiple code rates.This paper focuses on the 5G LDPC coding and decoding algorithm,optimizes the coding and decoding scheme from the perspective of FPGA hardware,and designs and implements a high-throughput 5G LDPC codec based on FPGA compatible with multiple code rates.For the encoder design,this paper focuses on the encoding algorithm suitable for 5G LDPC check matrix,and optimizes the encoding steps from the perspective of hardware to reduce the repeated reading of data.Based on the feature that the 5G LDPC check matrix can be divided into multiple cyclic unit matrices,the cyclic unit matrix size is used as the unit to encode at the same time,and the traditional single-bit encoding is converted into multi-bit encoding.The encoder structure is further designed to be a fully parallel structure,and in the case of low code rate,the encoder has a great throughput rate.Aiming at the decoder design,this paper introduces a variety of LDPC decoding algorithms,and focuses on a dual-layer scheduling decoder architecture based on hierarchical message passing.Based on this architecture,a high-throughput 5G LDPC decoding algorithm is designed.encoder.Aiming at the characteristics of traditional single-layer scheduling layered LDPC decoder with high decoding delay and low throughput at low bit rate,this paper proposes a layered message passing method suitable for 5G LDPC.Scheduling decoder architecture,the scheme divides the adjacent two layers of the parity check matrix into a pre-calculation layer and a waiting layer to solve the problem of conflicting variable nodes in double-layer decoding.Further,in order to reduce the input and output delay of variable nodes of each layer during decoding,and at the same time maintain the accuracy of the decoding of the precomputed layer and the waiting layer,this paper rearranges the input and output order of the variable nodes of each layer during the calculation,so that the variable nodes of each layer are calculated.The input and output are more pipelined and the clock utilization efficiency is improved.That is to say,after each group of calculations is finished,and the updated nodes are output,the input of the next group of nodes can be started,which makes the work of the decoder more streamlined.Compared with the traditional single-layer scheduling decoder architecture,this scheme significantly improves the decoder throughput regardless of high bit rate or low bit rate.Especially in the case of low bit rate,the double-layer scheduling scheme designed in this paper The decoder throughput is 2.4 times that of single-layer scheduling.