Research On And Design Of S-Band Low Phase Noise Frequency Synthesizer

High-performance frequency synthesizer,as one of the core modules of RF front-end,has a wide range of application scenarios in wireless communication,navigation,radar and other fields.The research and design of frequency synthesizer with low phase noise and high robustness is of great significance to ensure low bit error rate data transmission and radar detection accuracy.As an implementation scheme of frequency synthesizer,sub sampling phase-locked loop can significantly suppress the noise contribution of sub sampling phase detector and sub sampling charge pump,and has outstanding advantages in low phase noise performance.Taking sub sampling phase-locked loop as the research object,this paper focuses on the optimization technology of phase noise and locking range of S-band sub sampling phase-locked loop,which is of great significance for supporting high-speed wireless communication and high-precision radar detection.Aiming at the phase noise and locking range of the S-band sub sampling phase-locked loop,this paper studies the dual-mode low phase noise voltage-controlled oscillator,sub sampling phase detector,and loop switching schemes and so on.First,the phase noise transfer function of the sub sampling PLL system is modeled and analyzed,and the loop parameters with low phase noise performance are obtained to guide the design and optimization of the circuit modules.Aiming at the problem that the phase noise of the voltage-controlled oscillator deteriorates the out-of-band phase noise performance of the sub sampling phase-locked loop,a transformer-coupled dual-mode voltage-controlled oscillator is studied and designed,which has an wide frequency tuning range and good phase noise.The use of capacitive coupling can ensure that the voltage-controlled oscillator has a more balanced noise performance in the whole frequency band.Cadence and electromagnetic hybrid simulation results show that the output phase noise is less than-102 d Bc/Hz@100KHz,-130 d Bc/Hz@1MHz in the frequency range of 2.2-4.4 GHz,the power consumption is less than 33m W,and it has great advantages in bandwidth and phase noise performance,which lays a good technical foundation for the phase noise optimization of sub sampling phase-locked loop.The sub sampling phase detector is realized by NMOS switched capacitor.Aiming at the problem that the BFSK effect of the sampling circuit worsens the reference spurs of the sub sampling phase-locked loop,the dummy module controlled by the inverted clock signal is added to ensure the constant capacitance of the output end of the voltage-controlled oscillator and suppress the spurs problem caused by the change of the oscillator frequency.The sub sampling charge pump circuit uses the pulse signal generation circuit to control the charge pump gain,which is conducive to the integration of sub sampling phase-locked loop filter.Through joint simulation with sub sampling phase detector,an approximate-229d Bv/Hz@1MHz phase noise is obtained.Aiming at the mismatch problem caused by the non ideal effect of the charge pump in frequency locked loop,the analysis and optimization method of the charge pump with low current mismatch is studied,and a source-switched charge pump with an adjustable current array is designed.The complementary transistor switch and unit gain operational amplifier structure are used to obtain high-precision charge pump current.The current mismatch is less than 0.2%,and the current noise value of PFD and CP joint simulation is-222.9 d BA/Hz@100KHz,-224.0 d BA/Hz@1MHz.The charge pump has good matching characteristics and noise characteristics,which strongly supports the phase noise optimization of sub sampling phase-locked loop.In view of the possible instability of sub sampling phase-locked loop in the switching between frequency locked loop and sub sampling loop,this paper proposes a soft switching scheme of sub sampling phase-locked loop.By adding the loop gain switch control circuit,the fluctuation of gain and phase margin in the whole switching process is reduced,so as to greatly improve the stability.Based on SMIC 55 nm process,the layout design and system simulation of sub sampling phase-locked loop are completed on Cadence platform.The frequency locking range of phase-locked loop is 2.2-4.4 GHz,the overall DC power consumption is 36 m W,the chip area is 0.51 mm~2,and the locking time is less than 5μs.Noise fitting is performed at 4.4GHz frequency,and the output phase noise of the sub sampling phase-locked loop is-117d Bc/Hz@100KHz,-125 d Bc/Hz@1MHz,which is excellent in the entire S-band.In this research work,the optimization methods and technologies of phase noise and locking range of sub sampling phase-locked loop are discussed in detail from the aspects of sub sampling phase-locked loop system modeling,key circuit module optimization and loop stability.The simulation results verify the effectiveness of the research and provide a good guiding idea for the research and design of sub sampling phase-locked loop.